Datasheet > CY7C1299A

CY7C1299A

更新时间： 2024-01-12 21:06:56

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
11页	138K
描述
32K x 36 Dual I/O Dual Address Synchronous SRAM

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CY7C1299A 数据手册

CY7C1299A

32K x 36 Dual I/O Dual Address Synchronous SRAM

The CY7C1299A allows the user to concurrently perform

Reads, Writes, or pass-through cycles in combination on the

Features

• Fast clock speed: 100 and 83 MHz

• Fast access times: 5.0/6.0 ns max.

• Single clock operation

• Single 3.3V –5% and +5% power supply V_CC

• Separate V_CCQfor output buffer

• Two chip enables for simple depth expansion

• Address, data input, CE1, CE2, PTX, PTY, WEX, WEY,

and data output registers on-chip

• Concurrent Reads and Writes

• Two bidirectional data buses

• Can be configured as separate I/O

• Pass-through feature

• Asynchronous output enables (OEX, OEY)

• LVTTL-compatible I/O

two data ports. The two address ports (AX, AY) determine the

read or write locations for their respective data ports (DQX,

DQY).

All input pins except output enable pins (OEX, OEY) are gated

by registers controlled by a positive-edge-triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, depth-expansion chip enables (CE1, CE2),

pass-through controls (PTX and PTY), and read-write control

(WEX and WEY). The pass-through feature allows data to be

passed from one port to the other, in either direction. The PTX

input must be asserted to pass data from port X to port Y. The

PTY will likewise pass data from port Y to port X. A

pass-through operation takes precedence over a read

operation.

For the case when AX and AY are the same, certain protocols

are followed. If both ports are read, the reads occur normally.

If one port is written and the other is read, the read from the

array will occur before the data is written. If both ports are

written, only the data on DQY will be written to the array.

• Self-timed Write

• Automatic power-down

• 176-pin TQFP package

The CY7C1299A operates from a +3.3V power supply. All

inputs and outputs are LVTTL compatible. These dual I/O, dual

address synchronous SRAMs are well suited for ATM,

Ethernet switches, routers, cell/frame buffers, SNA switches

and shared memory applications.

Functional Description

The CY7C1299A SRAM integrates 32,768 × 36 SRAM cells

with advanced synchronous peripheral circuitry. It employs

high-speed, low-power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1299A needs one extra cycle after power for proper

power-on reset. The extra cycle is needed after V_CCis stable

on the device. This device is available in a 176-pin TQFP

package.

Logic Block Diagram^[1]

CE1#

CE2

OEy#

Note:

1. For 32K x 36 devices, AX and AY are 15-bit-wide buses.

Cypress Semiconductor Corporation

Document #: 38-05138 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised May 14, 2003

12 3 4 5 6 7...11

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与CY7C1299A相关器件

型号	品牌	获取价格	描述	数据表
CY7C1299A-100AC	CYPRESS	获取价格	32K x 36 Dual I/O Dual Address Synchronous SRAM
CY7C1299A-83AC	CYPRESS	获取价格	32K x 36 Dual I/O Dual Address Synchronous SRAM
CY7C129DV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C129EV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C130	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C130BV18*	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C130BV25*	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C130DV25*	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C130_05	CYPRESS	获取价格	1K x 8 Dual-Port Static RAM
CY7C130_12	CYPRESS	获取价格	1 K Ã 8 Dual-Port Static RAM

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