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CY7C130_05

更新时间： 2024-01-05 22:59:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 573K
描述
1K x 8 Dual-Port Static RAM

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中文翻译

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CY7C130_05 数据手册

 浏览型号CY7C130_05的Datasheet PDF文件第2页浏览型号CY7C130_05的Datasheet PDF文件第3页浏览型号CY7C130_05的Datasheet PDF文件第4页浏览型号CY7C130_05的Datasheet PDF文件第5页浏览型号CY7C130_05的Datasheet PDF文件第6页浏览型号CY7C130_05的Datasheet PDF文件第7页 
CY7C130/CY7C131  
CY7C140/CY7C141  
1K x 8 Dual-Port Static RAM  
Features  
Functional Description  
• True Dual-Ported memory cells which allow simulta-  
neous reads of the same memory location  
The CY7C130/CY7C131/CY7C140 and CY7C141 are  
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports  
are provided permitting independent access to any location in  
memory. The CY7C130/ CY7C131 can be utilized as either a  
standalone 8-bit dual-port static RAM or as a master dual-port  
RAM in conjunction with the CY7C140/CY7C141 slave  
dual-port device in systems requiring 16-bit or greater word  
widths. It is the solution to applications requiring shared or  
buffered data, such as cache memory for DSP, bit-slice, or  
multiprocessor designs.  
• 1K x 8 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
• Low operating power: ICC = 110 mA (max.)  
• Fully asynchronous operation  
• Automatic power-down  
Each port has independent control pins; chip enable (CE),  
write enable (R/W), and output enable (OE). Two flags are  
provided on each port, BUSY and INT. BUSY signals that the  
port is trying to access the same location currently being  
accessed by the other port. INT is an interrupt flag indicating  
that data has been placed in a unique location (3FF for the left  
port and 3FE for the right port). An automatic power-down  
feature is controlled independently on each port by the chip  
enable (CE) pins.  
• Master CY7C130/CY7C131 easily expands data bus  
width to 16 or more bits using slave CY7C140/CY7C141  
• BUSY output flag on CY7C130/CY7C131; BUSY input  
on CY7C140/CY7C141  
• INT flag for port-to-port communication  
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC,  
52-Pin TQFP.  
• Pb-Free packages available  
The CY7C130 and CY7C140 are available in 48-pin DIP. The  
CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin  
Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP.  
Logic Block Diagram  
Pin Configurations  
R/W  
L
R/W  
R
CE  
L
CE  
R
DIP  
Top View  
OE  
L
OE  
R
V
48  
CE  
R/W  
BUSY  
CC  
CE  
1
L
L
L
47  
46  
45  
44  
R
R
2
3
4
5
6
R/W  
BUSY  
INT  
I/O  
I/O  
I/O  
7L  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
INT  
L
OE  
A
0L  
R
R
L
I/O  
0L  
0R  
OE  
A
43  
42  
R
0R  
[1]  
A
BUSY  
BUSY  
1L  
L
R
7
8
9
10  
11  
12  
A
A
A
41  
40  
2L  
1R  
2R  
A
3L  
A
A
A
9L  
0L  
9R  
0R  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
A
39  
38  
37  
36  
35  
34  
3R  
4L  
A
A
A
5L  
4R  
5R  
A
A
6L  
7C130  
A
A
13 7C140  
6R  
7L  
A
8L  
A
9L  
A
A
14  
15  
16  
17  
18  
7R  
8R  
I/O  
A
9R  
I/O  
33  
32  
31  
30  
29  
28  
27  
26  
25  
0L  
I/O  
1L  
ARBITRATION  
LOGIC  
7R  
I/O  
2L  
I/O  
3L  
I/O  
4L  
I/O  
6R  
I/O  
(7C130/7C131 ONLY)  
AND  
19  
20  
21  
22  
23  
24  
5R  
CE  
L
CE  
R
I/O  
4R  
I/O  
INTERRUPT LOGIC  
OE  
L
OE  
R
I/O  
3R  
I/O  
5L  
I/O  
6L  
I/O  
7L  
GND  
2R  
R/W  
R/W  
R
L
I/O  
1R  
I/O  
[2]  
0R  
[2]  
INT  
INT  
R
L
Note:  
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor  
CY7C140/CY7C141 (Slave): BUSY is input.  
2. Open drain outputs: pull-up resistor required.  
Cypress Semiconductor Corporation  
Document #: 38-06002 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 29, 2005  
1234567...19

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