Datasheet > CY7C1298F

CY7C1298F

更新时间： 2024-09-30 21:55:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	332K
描述
1-Mbit (64K x 18) Pipelined DCD Sync SRAM

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CY7C1298F 数据手册

CY7C1298F

1-Mbit (64K x 18) Pipelined DCD Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

The CY7C1298F SRAM integrates 65,536x18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

• 64K × 18-bit common I/O architecture

• 3.3V –5% and +10% core power supply (V_DD

)

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

• 3.3V I/O supply (V_DDQ

)

Control inputs (

and

ADSC ADSP

), Write Enables

ADV

(

, and

BW_[A:B]

), and Global Write (

). Asynchronous

BWE

• Fast clock-to-output times

— 3.5ns (for 166-MHz device)

— 4.0ns (for 133-MHz device)

inputs include the Output Enable ( ) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

• Provide high-performance 3-1-1-1 access rate

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• User-selectable burst counter supporting Intel^

ADV

Pentium^interleaved or linear burst sequences

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100-pin TQFP package and pinout

• “ZZ” Sleep Mode option

controlled by the byte write control inputs.

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

The CY7C1298F operates from a +3.3V core power supply

while all outputs operate with a +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

166 MHz

3.5

133 MHz

4.0

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

240

225

Shaded areas contain advance information. Please contact your local CYpress sales representative for availability of these parts.

Note:

1. . For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05417 Rev. *A

Revised April 7, 2004

12 3 4 5 6 7...15

中文翻译

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与CY7C1298F相关器件

型号	品牌	获取价格	描述	数据表
CY7C1298F-133AC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298F-133ACT	CYPRESS	获取价格	Standard SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1298F-133AXC	CYPRESS	获取价格	Standard SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1298H	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-100AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-100AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-133AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H-133AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1299A	CYPRESS	获取价格	32K x 36 Dual I/O Dual Address Synchronous SRAM
CY7C1299A-100AC	CYPRESS	获取价格	32K x 36 Dual I/O Dual Address Synchronous SRAM

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