CY7C12611KV18, CY7C12761KV18
CY7C12631KV18, CY7C12651KV18
36-Mbit QDR® II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Functional Description
■ Separate independent read and write data ports
❐ Supports concurrent transactions
The CY7C12611KV18, CY7C12761KV18, CY7C12631KV18,
and CY7C12651KV18 are 1.8 V Synchronous Pipelined SRAMs,
equipped with QDR® II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
■ 550 MHz clock for high bandwidth
■ 4-word burst for reducing address bus frequency
■ Double data rate (DDR) intrfaces on both read and write ports
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with four 8-bit words
(CY7C12611KV18), 9-bit words (CY7C12761KV18), 18-bit
words (CY7C12631KV18), or 36-bit words (CY7C12651KV18)
that burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
(Data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self timed writes
■ QDR® II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen
DOFF is asserted LOW
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self timed write circuitry.
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency, providing most current data
[1]
■ Core VDD = 1.8 V± 0.1 V; I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
These devices are down bonded from the 65 nm 72 M
QDRII+/DDRII+ devices and hence have the same IDD / ISB1
values and the same JTAG ID code as the equivalent 72 M
device options. For details refer to the application note AN53189,
65 nm Technology Interim QDRII +/ DDRII + SRAM device family
description.
■ High speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
■ Available in 165-ball Fine pitch ball grid array (FBGA) package
(13 x 15 x 1.4 mm)
Table 1. Selection Guide
550 500 450 400
■ Offered in both Pb-free and non Pb-free packages
Description
Unit
MHz MHz MHz MHz
■ Joint test action group (JTAG) 1149.1 compatible test access
port
Max operating frequency
Max operating current
550 500 450 400 MHz
x8 900 830 760 690 mA
x9 900 830 760 690
■ Phase locked loop (PLL) for accurate data placement
Configurations
x18 920 850 780 710
x36 1310 1210 1100 1000
With Read Cycle Latency of 2.5 cycles:
CY7C12611KV18 – 4 M x 8
CY7C12761KV18 – 4 M x 9
CY7C12631KV18 – 2 M x 18
CY7C12651KV18 – 1 M x 36
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4 V to V
.
DD
DDQ
Cypress Semiconductor Corporation
Document Number: 001-53193 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised February 2, 2011
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