CY7C1261V18-375BZC

更新时间： 2024-09-16 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	1259K
描述
36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C1261V18

CY7C1276V18

CY7C1263V18

CY7C1265V18

36-Mbit QDR™-II+ SRAM 4-Word

Burst Architecture (2.5 Cycle Read Latency)

Functional Description

Features

• Separate independent read and write data ports

— Supports concurrent transactions

The CY7C1261V18, CY7C1276V18, CY7C1263V18, and

CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Quad Data Rate-II+ (QDR-II+) architecture.

QDR-II+ architecture consists of two separate ports to access

the memory array. The read port has dedicated data outputs

to support read operations and the write port has dedicated

data inputs to support write operations. QDR-II+ architecture

has separate data inputs and data outputs to completely

eliminate the need to “turn around” the data bus required with

common IO devices. Each port is accessed through a common

address bus. Addresses for read and write addresses are

latched on alternate rising edges of the input (K) clock.

Accesses to the QDR-II+ read and write ports are completely

independent of one another. To maximize data throughput,

both read and write ports are equipped with Double Data Rate

(DDR) interfaces. Each address location is associated with

• 300 MHz to 400 MHz clock for high bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both read and write

ports (data transferred at 800 MHz) at 400 MHz

• Read latency of 2.5 clock cycles

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Singlemultiplexedaddressinputbuslatchesaddressinputs

for both read and write ports

four

8-bit

words

(CY7C1261V18),

9-bit

words

• Separate Port Selects for depth expansion

• Data valid pin (QVLD) to indicate valid data on the output

• Synchronous internally self-timed writes

(CY7C1276V18), 18-bit words (CY7C1263V18), or 36-bit

words (CY7C1265V18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K),

memory bandwidth is maximized while simplifying system

design by eliminating bus “turn-arounds”.

• Available in x8, x9, x18, and x36 configurations

• Full data coherency providing most current data

[1]

• Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

Depth expansion is accomplished with Port Selects for each

port. Port selects enable each port to operate independently.

• HSTL inputs and Variable drive HSTL output buffers

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both Pb-free and non Pb-free packages

• JTAG 1149.1 compatible test access port

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

• Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1261V18 – 4M x 8

CY7C1276V18 – 4M x 9

CY7C1263V18 – 2M x 18

CY7C1265V18 – 1M x 36

Selection Guide

400 MHz

400

375 MHz

333 MHz

333

300 MHz

300

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

375

1330

1240

1120

1040

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

DDQ

= 1.4V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-06366 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 14, 2007

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与CY7C1261V18-375BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1261V18-375BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1261V18-375BZXC	CYPRESS	获取价格	36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1261V18-375BZXI	CYPRESS	获取价格	36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1261V18-400BZC	CYPRESS	获取价格	36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1261V18-400BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1261V18-400BZXC	CYPRESS	获取价格	36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1261V18-400BZXI	CYPRESS	获取价格	36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1262XV18	CYPRESS	获取价格	36-Mbit QDRÂ® II Xtreme SRAM Two-Word Burst A
CY7C1262XV18-366BZXC	CYPRESS	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1262XV18-366BZXC	INFINEON	获取价格	Synchronous SRAM

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