Datasheet > CY7C1262XV18-450BZXC

CY7C1262XV18-450BZXC

更新时间： 2024-09-15 21:01:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
29页	1012K
描述
QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, FBGA-165

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1262XV18-450BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	1 week	风险等级：	2.31
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	450 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	37748736 bit
内存集成电路类型：	QDR SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	1.205 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	1.205 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	13 mm
Base Number Matches：	1

CY7C1262XV18-450BZXC 数据手册

浏览型号CY7C1262XV18-450BZXC的Datasheet PDF文件第2页

浏览型号CY7C1262XV18-450BZXC的Datasheet PDF文件第3页

浏览型号CY7C1262XV18-450BZXC的Datasheet PDF文件第4页

浏览型号CY7C1262XV18-450BZXC的Datasheet PDF文件第5页

浏览型号CY7C1262XV18-450BZXC的Datasheet PDF文件第6页

CY7C1262XV18

CY7C1264XV18

36-Mbit QDR^®II+ Xtreme SRAM Two-Word

Burst Architecture (2.5 Cycle Read Latency)

36-Mbit QDR^®II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.5 cycles:

CY7C1262XV18 – 2 M × 18

■ 450 MHz clock for high bandwidth

CY7C1264XV18 – 1 M × 36

■ Two-word burst for reducing address bus frequency

Functional Description

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 900 MHz) at 450 MHz

The CY7C1262XV18, and CY7C1264XV18 are 1.8 V

Synchronous Pipelined SRAMs, equipped with QDR^®II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turnaround” the data bus that

exists with common I/O devices. Access to each port is through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ Xtreme read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with two 18-bit

words (CY7C1262XV18), or 36-bit words (CY7C1264XV18) that

burst sequentially into or out of the device. Because data can be

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turnarounds”.

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR™-II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

■ Operates similar to QDR-I device with 1 cycle read latency

when DOFF is asserted LOW

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Available in x18, and x36 configurations

■ Full data coherency, providing most current data

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Core V_DD= 1.8 V ± 0.1 V; I/Os V_DDQ= 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in Pb-free packages

For a complete list of related documentation, click here.

■ JTAG 1149.1 compatible test access port

■ Phase-Locked Loop (PLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

450 MHz

450

366 MHz Unit

366

970

MHz

Maximum Operating Current

× 18

× 36

1205

1445

1165

Cypress Semiconductor Corporation

Document Number: 001-70327 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 22, 2017

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1262XV18-450BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C12631KV18	CYPRESS	获取价格	36-Mbit QDRÂ® II SRAM 4-Word Burst Architectu
CY7C1263KV18	CYPRESS	获取价格	36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1263KV18_12	CYPRESS	获取价格	36-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1263KV18-400BZC	CYPRESS	获取价格	36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1263KV18-400BZI	CYPRESS	获取价格	36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1263KV18-400BZXI	CYPRESS	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1263KV18-400BZXI	INFINEON	获取价格	Synchronous SRAM
CY7C1263KV18-500BZXC	CYPRESS	获取价格	36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1263KV18-550BZI	CYPRESS	获取价格	36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1263KV18-550BZXC	CYPRESS	获取价格	36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

与CY7C1262XV18-450BZXC相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

4
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

4
SL74HC10N：高性能三输入与非门解析
2024-09-03

83
AIC1781A 电池充电控制器深度解析
2024-09-03

75

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1262XV18-450BZXC

CY7C1262XV18-450BZXC 技术参数

CY7C1262XV18-450BZXC 数据手册

与CY7C1262XV18-450BZXC相关器件

与CY7C1262XV18-450BZXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1262XV18-450BZXC

CY7C1262XV18-450BZXC 技术参数

CY7C1262XV18-450BZXC 数据手册

与CY7C1262XV18-450BZXC相关器件

与CY7C1262XV18-450BZXC相关文章

您还可以找

您在本页遇到什么问题？