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CY7C1263V18-400BZXC PDF预览

CY7C1263V18-400BZXC

更新时间： 2024-11-23 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
28页 1259K
描述
36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C1263V18-400BZXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
针数：165Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.74
Is Samacsys：N最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：400 MHz
I/O 类型：SEPARATEJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：17 mm
内存密度：37748736 bit内存集成电路类型：QDR SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：1.5/1.8,1.8 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.32 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：1.33 mA最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：15 mmBase Number Matches：1

CY7C1263V18-400BZXC 数据手册

 浏览型号CY7C1263V18-400BZXC的Datasheet PDF文件第2页浏览型号CY7C1263V18-400BZXC的Datasheet PDF文件第3页浏览型号CY7C1263V18-400BZXC的Datasheet PDF文件第4页浏览型号CY7C1263V18-400BZXC的Datasheet PDF文件第5页浏览型号CY7C1263V18-400BZXC的Datasheet PDF文件第6页浏览型号CY7C1263V18-400BZXC的Datasheet PDF文件第7页 
CY7C1261V18  
CY7C1276V18  
CY7C1263V18  
CY7C1265V18  
36-Mbit QDR™-II+ SRAM 4-Word  
Burst Architecture (2.5 Cycle Read Latency)  
Functional Description  
Features  
• Separate independent read and write data ports  
— Supports concurrent transactions  
The CY7C1261V18, CY7C1276V18, CY7C1263V18, and  
CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,  
equipped with Quad Data Rate-II+ (QDR-II+) architecture.  
QDR-II+ architecture consists of two separate ports to access  
the memory array. The read port has dedicated data outputs  
to support read operations and the write port has dedicated  
data inputs to support write operations. QDR-II+ architecture  
has separate data inputs and data outputs to completely  
eliminate the need to “turn around” the data bus required with  
common IO devices. Each port is accessed through a common  
address bus. Addresses for read and write addresses are  
latched on alternate rising edges of the input (K) clock.  
Accesses to the QDR-II+ read and write ports are completely  
independent of one another. To maximize data throughput,  
both read and write ports are equipped with Double Data Rate  
(DDR) interfaces. Each address location is associated with  
• 300 MHz to 400 MHz clock for high bandwidth  
• 4-Word Burst for reducing address bus frequency  
• Double Data Rate (DDR) interfaces on both read and write  
ports (data transferred at 800 MHz) at 400 MHz  
• Read latency of 2.5 clock cycles  
• Two input clocks (K and K) for precise DDR timing  
— SRAM uses rising edges only  
• Echo clocks (CQ and CQ) simplify data capture in  
high-speed systems  
• Singlemultiplexedaddressinputbuslatchesaddressinputs  
for both read and write ports  
four  
8-bit  
words  
(CY7C1261V18),  
9-bit  
words  
• Separate Port Selects for depth expansion  
• Data valid pin (QVLD) to indicate valid data on the output  
• Synchronous internally self-timed writes  
(CY7C1276V18), 18-bit words (CY7C1263V18), or 36-bit  
words (CY7C1265V18) that burst sequentially into or out of the  
device. Because data can be transferred into and out of the  
device on every rising edge of both input clocks (K and K),  
memory bandwidth is maximized while simplifying system  
design by eliminating bus “turn-arounds”.  
• Available in x8, x9, x18, and x36 configurations  
• Full data coherency providing most current data  
[1]  
• Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD  
Depth expansion is accomplished with Port Selects for each  
port. Port selects enable each port to operate independently.  
• HSTL inputs and Variable drive HSTL output buffers  
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)  
• Offered in both Pb-free and non Pb-free packages  
• JTAG 1149.1 compatible test access port  
All synchronous inputs pass through input registers controlled  
by the K or K input clocks. All data outputs pass through output  
registers controlled by the K or K input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Delay Lock Loop (DLL) for accurate data placement  
Configurations  
With Read Cycle Latency of 2.0 cycles:  
CY7C1261V18 – 4M x 8  
CY7C1276V18 – 4M x 9  
CY7C1263V18 – 2M x 18  
CY7C1265V18 – 1M x 36  
Selection Guide  
400 MHz  
400  
375 MHz  
333 MHz  
333  
300 MHz  
300  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
375  
1330  
1240  
1120  
1040  
Note  
1. The QDR consortium specification for V  
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting  
DDQ  
V
= 1.4V to V  
.
DDQ  
DD  
Cypress Semiconductor Corporation  
Document Number: 001-06366 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 14, 2007  
[+] Feedback  
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