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CY7C109BN PDF预览

CY7C109BN

更新时间： 2024-11-06 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 453K
描述
128K x 8 Static RAM

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CY7C109BN 数据手册

 浏览型号CY7C109BN的Datasheet PDF文件第2页浏览型号CY7C109BN的Datasheet PDF文件第3页浏览型号CY7C109BN的Datasheet PDF文件第4页浏览型号CY7C109BN的Datasheet PDF文件第5页浏览型号CY7C109BN的Datasheet PDF文件第6页浏览型号CY7C109BN的Datasheet PDF文件第7页 
CY7C109BN  
CY7C1009BN  
128K x 8 Static RAM  
Features  
Functional Description[1]  
• High speed  
The CY7C109BN/CY7C1009BN is a high-performance  
CMOS static RAM organized as 131,072 words by 8 bits. Easy  
memory expansion is provided by an active LOW Chip Enable  
(CE1), an active HIGH Chip Enable (CE2), an active LOW  
Output Enable (OE), and three-state drivers. Writing to the  
device is accomplished by taking Chip Enable One (CE1) and  
Write Enable (WE) inputs LOW and Chip Enable Two (CE2)  
input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is  
then written into the location specified on the address pins (A0  
through A16).  
— tAA = 12 ns  
• Low active power  
— 495 mW (max. 12 ns)  
• Low CMOS standby power  
— 55 mW (max.) 4 mW  
• 2.0V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and OE options  
Reading from the device is accomplished by taking Chip  
Enable One (CE1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
The CY7C109BN is available in standard 400-mil-wide SOJ  
and 32-pin TSOP type I packages. The CY7C1009BN is  
available in a 300-mil-wide SOJ package. The CY7C1009BN  
and CY7C109BN are functionally equivalent in all other  
respects.  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
V
NC  
32  
31  
30  
1
CC  
A
16  
A
15  
CE  
2
3
4
A
14  
2
A
12  
29  
28  
WE  
5
A
7
A
6
A
5
A
A
A
13  
8
27  
26  
6
7
9
25  
24  
23  
22  
21  
A
A
8
9
10  
11  
12  
13  
A
4
3
11  
OE  
I/O  
0
A
A
A
10  
2
1
INPUT BUFFER  
CE  
I/O  
I/O  
1
7
6
A
I/O  
0
0
I/O  
I/O  
1
20  
19  
A
0
A
1
I/O  
I/O  
GND  
I/O  
1
5
14  
15  
16  
I/O  
I/O  
2
18  
17  
4
3
2
A
2
A
4
3
A
A
A
A
A
WE  
CE  
A
1
2
32  
31  
OE  
11  
I/O  
I/O  
I/O  
I/O  
3
4
5
512 x 256 x 8  
ARRAY  
A
A
9
8
10  
5
6
3
4
5
6
7
8
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CE  
I/O  
A
13  
7
A
7
8
I/O  
I/O  
6
5
A
2
15  
I/O  
I/O  
TSOP I  
4
3
V
Top View  
CC  
NC  
A
A
A
A
A
6
A
A
9
GND  
(not to scale)  
I/O  
10  
11  
12  
13  
14  
15  
16  
16  
2
6
7
POWER  
DOWN  
I/O  
1
COLUMN  
DECODER  
14  
12  
CE  
2
WE  
1
I/O  
0
CE  
A
0
7
I/O  
A
1
A
2
5
4
A
3
OE  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06430 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 1, 2006  
[+] Feedback  
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与CY7C109BN相关器件

型号 品牌 获取价格 描述 数据表
CY7C109BN_09 CYPRESS

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 		128K x 8 Static RAM
CY7C109BN-12VC ROCHESTER

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 		128KX8 STANDARD SRAM, 12ns, PDSO32, 0.400 INCH, SOJ-32
CY7C109BN-12VC CYPRESS

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 		128K x 8 Static RAM
CY7C109BN-12VCT CYPRESS

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 		Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, SOJ-32
CY7C109BN-12ZC CYPRESS

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 		128K x 8 Static RAM
CY7C109BN-12ZC ROCHESTER

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 		128KX8 STANDARD SRAM, 12ns, PDSO32, 8 X 20 MM, TSOP1-32
CY7C109BN-12ZCT CYPRESS

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 		Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32
CY7C109BN-12ZXC CYPRESS

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 		128K x 8 Static RAM
CY7C109BN-12ZXC ROCHESTER

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 		128KX8 STANDARD SRAM, 12ns, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY7C109BN-12ZXCT CYPRESS

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 		Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32

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