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CY7C109B-20ZXC PDF预览

CY7C109B-20ZXC

更新时间： 2024-09-15 13:01:15
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赛普拉斯 - CYPRESS 内存集成电路静态存储器光电二极管
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CY7C109B-20ZXC 数据手册

 浏览型号CY7C109B-20ZXC的Datasheet PDF文件第2页浏览型号CY7C109B-20ZXC的Datasheet PDF文件第3页浏览型号CY7C109B-20ZXC的Datasheet PDF文件第4页浏览型号CY7C109B-20ZXC的Datasheet PDF文件第5页浏览型号CY7C109B-20ZXC的Datasheet PDF文件第6页浏览型号CY7C109B-20ZXC的Datasheet PDF文件第7页 
009B  
CY7C109B  
CY7C1009B  
128K x 8 Static RAM  
put Enable (OE), and three-state drivers. Writing to the device  
is accomplished by taking Chip Enable One (CE1) and Write  
Enable (WE) inputs LOW and Chip Enable Two (CE2) input  
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then  
written into the location specified on the address pins (A0  
through A16).  
Features  
• High speed  
— tAA = 12 ns  
• Low active power  
— 495 mW (max. 12 ns)  
Reading from the device is accomplished by taking Chip En-  
able One (CE1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under  
these conditions, the contents of the memory location speci-  
fied by the address pins will appear on the I/O pins.  
• Low CMOS standby power  
— 55 mW (max.) 4 mW  
• 2.0V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and OEoptions  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
Functional Description  
The CY7C109B is available in standard 400-mil-wide SOJ and  
32-pin TSOP type I packages. The CY7C1009B is available in  
300-mil-wide SOJ package. The CY7C1009B and  
CY7C109B are functionally equivalent in all other respects.  
The CY7C109B / CY7C1009B is a high-performance CMOS  
static RAM organized as 131,072 words by 8 bits. Easy mem-  
ory expansion is provided by an active LOW Chip Enable  
(CE1), an active HIGH Chip Enable (CE2), an active LOW Out-  
a
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
V
NC  
32  
31  
30  
1
CC  
A
16  
A
15  
2
3
A
14  
CE  
2
A
4
12  
29  
28  
WE  
5
A
A
A
A
13  
A
8
A
7
27  
26  
6
6
5
7
9
25  
24  
23  
22  
21  
A
A
3
8
9
10  
11  
12  
13  
A
4
11  
OE  
I/O  
A
A
10  
2
0
A
1
CE  
I/O  
I/O  
INPUT BUFFER  
1
7
6
A
0
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
20  
19  
1
A
0
A
1
I/O  
5
14  
15  
16  
I/O  
I/O  
18  
17  
4
2
A
2
GND  
3
109B–2  
A
3
4
A
A11  
A9  
A8  
A13  
WE  
CE2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
1
2
32  
31  
OE  
A10  
CE  
I/O  
I/O  
I/O  
3
4
5
512 x 256 x 8  
ARRAY  
A
5
6
3
4
5
6
7
8
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
GND  
I/O2  
I/O1  
I/O0  
A0  
A
7
8
A
TSOP I  
Top View  
9
(not to scale)  
I/O  
10  
11  
12  
13  
14  
15  
16  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
1
2
CE  
I/O  
WE  
A1  
A2  
A3  
109B–1  
OE  
109B–3  
Selection Guide  
7C109B-12  
7C1009B-12  
7C109B-15  
7C1009B-15  
7C109B-20  
7C1009B-20  
7C109B-25  
7C1009B-25  
7C109B-35  
7C1009B-35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
12  
90  
10  
15  
80  
10  
20  
75  
10  
25  
70  
10  
35  
60  
10  
Maximum CMOS Standby Current (mA)  
Low Power Version  
2
2
2
-
-
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05038 Rev. **  
Revised August 24, 2001  
1234567...12

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