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CY7C1069AV33-8ZI PDF预览

CY7C1069AV33-8ZI

更新时间: 2024-11-28 22:25:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 252K
描述
2M x 8 Static RAM

CY7C1069AV33-8ZI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.83Is Samacsys:N
最长访问时间:8 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G54JESD-609代码:e0
长度:22.415 mm内存密度:16777216 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端子数量:54字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):235电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.05 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

CY7C1069AV33-8ZI 数据手册

 浏览型号CY7C1069AV33-8ZI的Datasheet PDF文件第2页浏览型号CY7C1069AV33-8ZI的Datasheet PDF文件第3页浏览型号CY7C1069AV33-8ZI的Datasheet PDF文件第4页浏览型号CY7C1069AV33-8ZI的Datasheet PDF文件第5页浏览型号CY7C1069AV33-8ZI的Datasheet PDF文件第6页浏览型号CY7C1069AV33-8ZI的Datasheet PDF文件第7页 
CY7C1069AV33  
2M x 8 Static RAM  
device is accomplished by enabling the chip (by taking CE1  
LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.  
Features  
• High speed  
Reading from the device is accomplished by enabling the chip  
(CE1 LOW and CE2 HIGH) as well as forcing the Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.  
See the truth table at the back of this data sheet for a complete  
description of Read and Write modes.  
— tAA = 8, 10, 12 ns  
• Low active power  
— 1080 mW (max.)  
• Operating voltages of 3.3 ± 0.3V  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1 and CE2 features  
The input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a Write operation (CE1 LOW, CE2 HIGH, and WE  
LOW).  
The CY7C1069AV33 is available in a 54-pin TSOP II package  
with center power and ground (revolutionary) pinout, and a  
48-ball fine-pitch ball grid array (FBGA) package.  
Functional Description  
The CY7C1069AV33 is a high-performance CMOS Static  
RAM organized as 2,097,152 words by 8 bits. Writing to the  
Logic Block Diagram  
Pin Configuration  
TSOP II  
Top View  
1
54 NC  
NC  
CC  
INPUT BUFFER  
V
53  
52  
51  
50  
V
NC  
I/O  
2
3
4
5
6
SS  
NC  
A
0
A
1
I/O  
6
5
V
V
CC  
SS  
A
2
I/O  
49 I/O  
7
4
A
4
3
A
4
48  
47  
A
5
I/O –I/O  
7
2M x 8  
ARRAY  
0
7
A
A
A
8
3
6
A
5
6
4096 x 4096  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
A
2
A
7
9
A
A
10  
11  
12  
13  
A
8
1
A
7
A
A
0
9
A
8
A
NC  
NC  
9
CE  
OE  
1
V
V
CC  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
SS  
WE  
DNU  
WE  
CE  
COLUMN  
DECODER  
CE  
A
20  
2
2
OE  
CE  
A
19  
A
10  
1
A
18  
A
11  
A
12  
A
13  
A
17  
A
16  
A
15  
A
14  
I/O  
V
I/O  
V
0
3
CC  
SS  
24  
25  
26  
27  
I/O  
I/O  
2
1
30 NC  
29  
NC  
V
V
SS  
CC  
28  
NC  
NC  
Selection Guide  
–8  
–10  
10  
–12  
12  
Unit  
ns  
Maximum Access Time  
8
Maximum Operating Current  
Commercial  
Industrial  
300  
300  
50  
275  
275  
50  
260  
260  
50  
mA  
Maximum CMOS Standby Current  
Commercial/Industrial  
mA  
Cypress Semiconductor Corporation  
Document #: 38-05255 Rev. *D  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised February 10, 2003  

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