Datasheet > CY7C1069G-10ZSXI

CY7C1069G-10ZSXI

更新时间： 2024-11-30 14:45:55

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
20页	608K
描述
Asynchronous SRAM

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CY7C1069G-10ZSXI 数据手册

CY7C1069G

CY7C1069GE

16-Mbit (2M words × 8 bit) Static RAM

with Error-Correcting Code (ECC)

16-Mbit (2M words

× 8 bit) Static RAM with Error-Correcting Code (ECC)

processor in the case of an ECC error-detection and correction

event.

Features

■ High speed

❐ t_AA= 10 ns

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₂₀).

■ Embedded error-correcting code (ECC) for single-bit error

correction

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. Under these conditions, the contents of the

memory location specified by the address pins will appear on the

I/O pins. See Truth Table – CY7C1069G/CY7C1069GE on page

14 for a complete description of Read and Write modes. The

input and output pins (I/O₀through I/O₇) are placed in a high

impedance state when the device is deselected (CE₁HIGH or

CE₂LOW), the outputs are disabled (OE HIGH), or during a write

operation (CE₁LOW, CE₂HIGH, and WE LOW).

■ Low active and standby currents

❐ I_CC= 90 mA typical at 100 MHz

❐ I_SB2= 20 mA typical

■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V

to 5.5 V

■ 1.0-V data retention

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ ERR pin to indicate 1-bit error detection and correction

On CY7C1069GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

■ Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA

packages

assertion of the ERR output (ERR = High) ^[1]

All I/Os (I/O₀through I/O₇) are placed in a high impedance state

when the device is deselected (CE₁HIGH or CE₂LOW), and

control signals are de-asserted (CE₁/ CE₂, OE, WE).

CY7C1069G and CY7C1069GE devices are available in a

54-pin TSOP II package with center power and ground

(revolutionary) pinout, and in a 48-ball VFBGA package.

Functional Description

The CY7C1069G and CY7C1069GE are dual chip enable

high-performance CMOS fast static RAM devices with

embedded ECC. The CY7C1069G device is available in

standard pin configurations. The CY7C1069GE device includes

a single bit error indication pin (ERR) that signals the host

For a complete list of related documentation, here.

Note

1. Automatic write back on error detection feature is not supported in this device.

Cypress Semiconductor Corporation

Document Number: 001-81539 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 5, 2017

12 3 4 5 6 7...20

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与CY7C1069G-10ZSXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1069G-10ZSXIT	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bit) Static RAM with E
CY7C1069G-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1069G30-10BVXI	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bit) Static RAM with E
CY7C1069G30-10BVXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1069G30-10BVXIT	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bit) Static RAM with E
CY7C1069G30-10BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1069G30-10ZSXI	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bit) Static RAM with E
CY7C1069G30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1069G30-10ZSXIT	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bit) Static RAM with E
CY7C1069G30-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM

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