CY7C1069GN
16-Mbit (2M × 8) Static RAM
16-Mbit (2M
× 8) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 10 ns
The CY7C1069GN is a high performance CMOS Static RAM
organized as 2,097,152 words by 8 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A20).
■ Low active power
❐ ICC = 90 mA at 100 MHz
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 20 mA (typical)
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the
I/O pins. See Truth Table on page 10 for a complete description
of Read and Write modes.
■ Operating voltages of 2.2 V to 3.6 V
■ 1.0 V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
The input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH, and WE LOW).
■ Available in Pb-free 54-pin thin small outline package (TSOP)
Type II and 48-ball very fine-pitch ball grid array (VFBGA)
packages.
The CY7C1069GN is available in a 54-pin TSOP II and a 48-ball
very fine-pitch ball grid array (VFBGA) package.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
I/O0 – I/O7
2 M x 8
A4
ARRAY
A5
A6
A7
A8
A9
WE
CE2
OE
COLUMN
DECODER
CE1
Cypress Semiconductor Corporation
Document Number: 002-00046 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 15, 2016