Datasheet > CY7C1069GN30-10ZSXI

CY7C1069GN30-10ZSXI

更新时间： 2024-11-06 14:56:39

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
15页	422K
描述
Asynchronous SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1069GN30-10ZSXI 数据手册

浏览型号CY7C1069GN30-10ZSXI的Datasheet PDF文件第2页

浏览型号CY7C1069GN30-10ZSXI的Datasheet PDF文件第3页

浏览型号CY7C1069GN30-10ZSXI的Datasheet PDF文件第4页

浏览型号CY7C1069GN30-10ZSXI的Datasheet PDF文件第5页

浏览型号CY7C1069GN30-10ZSXI的Datasheet PDF文件第6页

CY7C1069GN

16-Mbit (2M × 8) Static RAM

16-Mbit (2M

× 8) Static RAM

Features

Functional Description

■ High speed

❐ t_AA= 10 ns

The CY7C1069GN is a high performance CMOS Static RAM

organized as 2,097,152 words by 8 bits.

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₂₀).

■ Low active power

❐ I_CC= 90 mA at 100 MHz

■ Low complementary metal oxide semiconductor (CMOS)

standby power

❐ I_SB2= 20 mA (typical)

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. Under these conditions, the contents of the

memory location specified by the address pins will appear on the

I/O pins. See Truth Table on page 10 for a complete description

of Read and Write modes.

■ Operating voltages of 2.2 V to 3.6 V

■ 1.0 V data retention

■ Automatic power-down when deselected

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ Easy memory expansion with CE₁and CE₂features

The input and output pins (I/O₀through I/O₇) are placed in a high

impedance state when the device is deselected (CE₁HIGH or

CE₂LOW), the outputs are disabled (OE HIGH), or during a write

operation (CE₁LOW, CE₂HIGH, and WE LOW).

■ Available in Pb-free 54-pin thin small outline package (TSOP)

Type II and 48-ball very fine-pitch ball grid array (VFBGA)

packages.

The CY7C1069GN is available in a 54-pin TSOP II and a 48-ball

very fine-pitch ball grid array (VFBGA) package.

Logic Block Diagram

INPUT BUFFER

A₀

A₁

A₂

A₃

I/O₀– I/O₇

2 M x 8

A₄

ARRAY

A₅

A₆

A₇

A₈

A₉

CE₂

COLUMN

DECODER

CE₁

Cypress Semiconductor Corporation

Document Number: 002-00046 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 19, 2017

12 3 4 5 6 7...15

中文翻译

下载PDF

与CY7C1069GN30-10ZSXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1069GN30-10ZSXIT	CYPRESS	获取价格	16-Mbit (2M Ã 8) Static RAM
CY7C1069GN30-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C106A-12PC	ETC	获取价格	x4 SRAM
CY7C106A-15DMB	ETC	获取价格	x4 SRAM
CY7C106A-15PC	ETC	获取价格	x4 SRAM
CY7C106A-15VCR	CYPRESS	获取价格	Standard SRAM, 256KX4, 15ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28
CY7C106A-20DMB	ETC	获取价格	x4 SRAM
CY7C106A-20PC	ETC	获取价格	x4 SRAM
CY7C106A-25DMB	ETC	获取价格	x4 SRAM
CY7C106A-25PC	ETC	获取价格	x4 SRAM