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CY7C1069DV33-10BVXI PDF预览

CY7C1069DV33-10BVXI

更新时间: 2024-11-09 03:14:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
9页 386K
描述
16-Mbit (2M x 8) Static RAM

CY7C1069DV33-10BVXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA, BGA48,6X8,30针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41Factory Lead Time:1 week
风险等级:5.73Is Samacsys:N
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48JESD-609代码:e1
长度:9.5 mm内存密度:16777216 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:48字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
最大待机电流:0.025 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.175 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:8 mm
Base Number Matches:1

CY7C1069DV33-10BVXI 数据手册

 浏览型号CY7C1069DV33-10BVXI的Datasheet PDF文件第2页浏览型号CY7C1069DV33-10BVXI的Datasheet PDF文件第3页浏览型号CY7C1069DV33-10BVXI的Datasheet PDF文件第4页浏览型号CY7C1069DV33-10BVXI的Datasheet PDF文件第5页浏览型号CY7C1069DV33-10BVXI的Datasheet PDF文件第6页浏览型号CY7C1069DV33-10BVXI的Datasheet PDF文件第7页 
CY7C1069DV33  
PRELIMINARY  
16-Mbit (2M x 8) Static RAM  
Features  
Functional Description  
• High speed  
The CY7C1069DV33 is a high-performance CMOS Static  
RAM organized as 2,097,152 words by 8 bits. Writing to the  
device is accomplished by enabling the chip (by taking CE1  
LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.  
— tAA = 10 ns  
• Low active power  
— ICC = 125 mA @ 10 ns  
Reading from the device is accomplished by enabling the chip  
(CE1 LOW and CE2 HIGH) as well as forcing the Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.  
See the truth table at the back of this data sheet for a complete  
description of Read and Write modes.  
• Low CMOS standby power  
— ISB2 = 25 mA  
• Operating voltages of 3.3 ± 0.3V  
• 2.0V data retention  
The input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a Write operation (CE1 LOW, CE2 HIGH, and WE  
LOW).  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1 and CE2 features  
The CY7C1069DV33 is available in a 54-pin TSOP II package  
with center power and ground (revolutionary) pinout, and a  
48-ball very fine-pitch ball grid array (VFBGA) package.  
• Available in Pb-free 54-pin TSOP II package and 48-ball  
VFBGA packages  
Logic Block Diagram  
Pin Configuration  
TSOP II  
Top View  
INPUT BUFFER  
NC  
1
2
3
4
5
6
54  
53  
NC  
CC  
V
V
SS  
NC  
52  
51  
50  
NC  
A
0
I/O  
I/O  
6
5
A
1
V
V
CC  
SS  
A
I/O  
49 I/O  
7
4
2
48  
47  
A
5
A
7
4
A
3
I/O0–I/O7  
2M x 8  
A
A
8
3
6
A
4
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
A
A
7
ARRAY  
9
2
A
A
5
10  
11  
12  
A
8
1
A
A
A
9
6
0
NC  
NC  
CE1 13  
CC  
14  
WE  
CE2  
A
7
OE  
A
8
V
V
SS  
A
9
NC  
15  
A
20  
16  
A
19  
A
10  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
A
18  
A
11  
WE  
CE2  
OE  
A
17  
A
13  
COLUMN  
DECODER  
12  
A
A
15  
16  
A
A
14  
I/O  
I/O  
0
3
V
V
CC  
SS  
I/O  
NC  
V
CE1  
I/O  
2
1
NC  
V
CC  
SS  
NC  
NC  
Selection Guide  
–10  
10  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
125  
25  
mA  
mA  
Maximum CMOS Standby Current  
Cypress Semiconductor Corporation  
Document #: 38-05478 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 14, 2006  
[+] Feedback  

CY7C1069DV33-10BVXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1069DV33-10BVXIT CYPRESS

完全替代

Standard SRAM, 2MX8, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48
CY7C1069G30-10BVXI CYPRESS

类似代替

16-Mbit (2M words × 8 bit) Static RAM with E

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