Datasheet > CY7C1062AV25

CY7C1062AV25

更新时间： 2024-09-15 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	284K
描述
512K x 32 Static RAM

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CY7C1062AV25 数据手册

CY7C1062AV25

512K x 32 Static RAM

Features

Functional Description

• High speed

The CY7C1062AV25 is a high-performance CMOS Static

RAM organized as 524,288 words by 32 bits.

— t_AA= 10 ns

Writing to the device is accomplished by enabling the chip

(CE_1,CE₂and CE₃LOW) and forcing the Write Enable (WE)

input LOW. If Byte Enable A (B_A) is LOW, then data from I/O

pins (I/O₀through I/O₇), is written into the location specified on

the address pins (A₀through A₁₈). If Byte Enable B (B_B) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written into

the location specified on the address pins (A₀through A₁₈).

Likewise, B_Cand B_Dcorrespond with the I/O pins I/O₁₆to I/O₂₃

and I/O₂₄to I/O₃₁, respectively.

• Low active power

— 745 mW (max.)

• Operating voltages of 2.5 ± 0.2V

• 1.5V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE₁, CE₂, and CE₃

features

Reading from the device is accomplished by enabling the chip

(CE_1,CE₂, and CE₃LOW) while forcing the Output Enable

(OE) LOW and Write Enable (WE) HIGH. If the first Byte

Enable (B_A) is LOW, then data from the memory location

specified by the address pins will appear on I/O₀to I/O₇. If Byte

Enable B (B_B) is LOW, then data from memory will appear on

I/O₈to I/O₁₅. Similarly, B_cand B_Dcorrespond to the third and

fourth bytes. See the truth table at the back of this data sheet

for a complete description of read and write modes.

• Available in non Pb-free 119-ball pitch ball grid array

package

The input/output pins (I/O₀through I/O₃₁) are placed in a

high-impedance state when the device is deselected (CE_1,

CE₂or CE₃HIGH), the outputs are disabled (OE HIGH), the

byte selects are disabled (B_A-DHIGH), or during a write

operation (CE_1,CE₂, and CE₃LOW, and WE LOW).

The CY7C1062AV25 is available in a 119-ball pitch ball grid

array (PBGA) package.

CE₁

CE₂

Logic Block Diagram

CE₃

INPUT BUFFERS

B_A

B_B

B_C

B_D

512K x 32

ARRAY

I/O₀–I/O₃₁

COLUMN

DECODER

Cypress Semiconductor Corporation

Document #: 38-05333 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 10, 2006

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与CY7C1062AV25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1062AV25-10BGC	CYPRESS	获取价格	512K x 32 Static RAM
CY7C1062AV25-10BGI	CYPRESS	获取价格	512K x 32 Static RAM
CY7C1062AV25-12BGC	CYPRESS	获取价格	Standard SRAM, 512KX32, 12ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1062AV25-12BGI	ROCHESTER	获取价格	Standard SRAM, 512KX32, 12ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1062AV25-8BGC	CYPRESS	获取价格	Standard SRAM, 512KX32, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1062AV25-8BGI	CYPRESS	获取价格	Standard SRAM, 512KX32, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1062AV33	CYPRESS	获取价格	The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bi
CY7C1062AV33_06	CYPRESS	获取价格	512K x 32 Static RAM
CY7C1062AV33-10BGC	CYPRESS	获取价格	The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bi
CY7C1062AV33-10BGI	CYPRESS	获取价格	The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bi

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