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CY7C1062DV33-10BGI PDF预览

CY7C1062DV33-10BGI

更新时间: 2024-11-26 12:49:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
15页 504K
描述
16-Mbit (512 K x 32) Static RAM

CY7C1062DV33-10BGI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数:119Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.82Is Samacsys:N
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:16777216 bit
内存集成电路类型:STANDARD SRAM内存宽度:32
湿度敏感等级:3功能数量:1
端口数量:1端子数量:119
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX32
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):220认证状态:Not Qualified
座面最大高度:2.4 mm最大待机电流:0.025 A
最大压摆率:0.175 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

CY7C1062DV33-10BGI 数据手册

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CY7C1062DV33  
16-Mbit (512 K × 32) Static RAM  
16-Mbit (512  
K × 32) Static RAM  
Features  
Functional Description  
High speed  
tAA = 10 ns  
The CY7C1062DV33 is a high performance CMOS Static RAM  
organized as 524,288 words by 32 bits.  
To write to the device, take Chip Enables (CE1, CE2, and CE3  
LOW) and Write Enable (WE) input LOW. If Byte Enable A (BA)  
is LOW, then data from I/O pins (I/O0 through I/O7) is written into  
the location specified on the address pins (A0 through A18). If  
Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A18). Likewise, BC and BD correspond with the I/O  
pins I/O16 to I/O23 and I/O24 to I/O31, respectively.  
Low active power  
ICC = 175 mA at 100 MHz  
Low complementary metal oxide semiconductor (CMOS)  
standby power  
ISB2 = 25 mA  
Operating voltages of 3.3 ± 0.3 V  
2.0 V data retention  
To read from the device, take Chip Enables (CE1, CE2, and CE3  
LOW) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If the first BA is LOW, then data from the  
memory location specified by the address pins appear on I/O0 to  
I/O7. If BB is LOW, then data from memory appears on I/O8 to  
I/O15. Likewise, Bc and BD correspond to the third and fourth  
bytes. See Truth Table on page 10 for a complete description of  
read and write modes.  
Automatic power down when deselected  
Transistor-transistor logic (TTL) compatible inputs and outputs  
Easy memory expansion with CE1, CE2, and CE3 features  
Available in Pb-free 119-ball plastic ball grid array (PBGA)  
package  
The input and output pins (I/O0 through I/O31) are placed in a  
high impedance state when the device is deselected (CE1, CE2,  
or CE3 HIGH), the outputs are disabled (OE HIGH), the byte  
selects are disabled (BA-D HIGH), or during a write operation  
(CE1, CE2 and CE3 LOW and WE LOW).  
Logic Block Diagram  
WE  
CE1  
CE2  
CE3  
INPUT BUFFERS  
OE  
BA  
BB  
BC  
BD  
512 K x 32  
ARRAY  
I/O0–I/O31  
A(9:0)  
COLUMN  
DECODER  
A(18:10)  
Cypress Semiconductor Corporation  
Document Number: 38-05477 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 20, 2011  
[+] Feedback  

CY7C1062DV33-10BGI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1062DV33-10BGXIT CYPRESS

完全替代

Standard SRAM, 512KX32, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTI
CY7C1062DV33-10BGIT CYPRESS

完全替代

Standard SRAM, 512KX32, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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