Datasheet > CY7C1062DV33_07

CY7C1062DV33_07

更新时间： 2024-09-16 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	459K
描述
16-Mbit (512K X 32) Static RAM

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中文翻译

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CY7C1062DV33_07 数据手册

CY7C1062DV33

16-Mbit (512K X 32) Static RAM

Features

Functional Description

■ High speed

❐ t_AA= 10 ns

The CY7C1062DV33 is a high performance CMOS Static RAM

organized as 524,288 words by 32 bits.

To write to the device, take Chip Enables (CE_1,CE_2,and CE₃

LOW) and Write Enable (WE) input LOW. If Byte Enable A (B_A)

is LOW, then data from IO pins (IO₀through IO₇) is written into

the location specified on the address pins (A₀through A₁₈). If

Byte Enable B (B_B) is LOW, then data from IO pins (IO₈through

IO₁₅) is written into the location specified on the address pins (A₀

through A₁₈). Likewise, B_Cand B_Dcorrespond with the IO pins

IO₁₆to IO₂₃and IO₂₄to IO₃₁, respectively.

■ Low active power

❐ I_CC= 175 mA at 10 ns

■ Low CMOS standby power

❐ I_SB2= 25 mA

■ Operating voltages of 3.3 ± 0.3V

■ 2.0V data retention

To read from the device, take Chip Enables (CE_1,CE₂, and CE₃

LOW), and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If the first Byte Enable (B_A) is LOW, then

data from the memory location specified by the address pins

appear on IO₀to IO₇. If Byte Enable B (B_B) is LOW, then data

from memory appears on IO₈to IO₁₅. Likewise, B_cand B_Dcorre-

spond to the third and fourth bytes. For more information, see

Truth Table on page 9 for a complete description of read and

write modes.

■ Automatic power down when deselected

■ TTL compatible inputs and outputs

■ Easy memory expansion with CE₁, CE₂, and CE₃features

■ Available in Pb-free 119-Ball PBGA package

The input and output pins (IO₀through IO₃₁) are placed in a high

impedance state when the device is deselected (CE_1,CE_2,or

CE₃HIGH), the outputs are disabled (OE HIGH), the byte selects

are disabled (B_A-DHIGH), or during a write operation (CE_1,CE₂

and CE₃LOW, and WE LOW).

Logic Block Diagram

CE₁

CE₂

CE₃

INPUT BUFFERS

B_A

B_B

B_C

B_D

512K x 32

ARRAY

IO₀– IO₃₁

A_(9:0)

COLUMN

DECODER

A_(18:10)

Cypress Semiconductor Corporation

Document Number: 38-05477 Rev.*D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 06, 2007

12 3 4 5 6 7...11

中文翻译

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与CY7C1062DV33_07相关器件

型号	品牌	获取价格	描述	数据表
CY7C1062DV33-10BGI	CYPRESS	获取价格	16-Mbit (512 K x 32) Static RAM
CY7C1062DV33-10BGIT	CYPRESS	获取价格	Standard SRAM, 512KX32, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1062DV33-10BGXI	CYPRESS	获取价格	16-Mbit (512K X 32) Static RAM
CY7C1062DV33-10BGXIT	CYPRESS	获取价格	Standard SRAM, 512KX32, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTI
CY7C1062G	CYPRESS	获取价格	16-Mbit (512 K words Ã 32 bits) Static RAM w
CY7C1062G30-10BGXI	CYPRESS	获取价格	16-Mbit (512 K words Ã 32 bits) Static RAM w
CY7C1062G30-10BGXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1062G30-10BGXIT	CYPRESS	获取价格	16-Mbit (512 K words Ã 32 bits) Static RAM w
CY7C1062G30-10BGXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1062GE	CYPRESS	获取价格	16-Mbit (512 K words Ã 32 bits) Static RAM w

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