Datasheet > CY7C1062GE30-10BGXI

CY7C1062GE30-10BGXI

更新时间： 2024-11-28 14:56:47

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
20页	474K
描述
Asynchronous SRAM

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CY7C1062G

CY7C1062GE

16-Mbit(512Kwords×32bits)StaticRAM

with Error-Correcting Code (ECC)

16-Mbit (512

K words × 32 bits) Static RAM with Error-Correcting Code (ECC)

Features

Functional Description

■ High speed

❐ t_AA= 10 ns/15 ns

CY7C1062G and CY7C1062GE are high-performance CMOS

fast static RAM devices with embedded ECC. Both have three

chip enables, giving easy memory expansion features. The

CY7C1062GE device includes an error indication pin that signals

the host processor in the case of a single bit error-detection and

correction event.

■ Embedded error-correcting code (ECC) for single-bit error

correction

■ Low active and standby current

❐ I_CC= 90 mA typical

❐ I_SB2= 20 mA typical

To write to the device, take Chip Enables (CE₁, CE₂, and CE₃

LOW) and Write Enable (WE) input LOW. If Byte Enable A (B_A)

is LOW, then data from I/O pins (I/O₀through I/O₇) is written into

the location specified on the address pins (A₀through A₁₈). If

Byte Enable B (B_B) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₈). Likewise, B_Cand B_Dcorrespond with the I/O

pins I/O₁₆to I/O₂₃and I/O₂₄to I/O₃₁, respectively.

■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V

■ 1.0-V data retention

■ Automatic power-down when deselected

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ ERR pin to indicate 1-bit error detection and correction

To read from the device, take Chip Enables (CE₁, CE₂, and CE₃

LOW) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If the first B_Ais LOW, then data from the

memory location specified by the address pins appear on I/O₀to

I/O₇. If B_Bis LOW, then data from memory appears on I/O₈to

I/O₁₅. Likewise, B_Cand B_Dcorrespond to the third and fourth

bytes. See Truth Table – CY7C1062G/CY7C1062GE on page 15

for a complete description of read and write modes.

■ Available in Pb-free 119-ball plastic ball grid array (PBGA)

package

The input and output pins (I/O₀through I/O₃₁) are placed in a

high-impedance state when the device is deselected (CE₁, CE₂,

or CE₃HIGH), the outputs are disabled (OE HIGH), the byte

selects are disabled (B_A-DHIGH), or during a write operation

(CE_1,CE₂and CE₃LOW and WE LOW).

On the CY7C1062GE device, the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = High)^[1]

CY7C1062G and CY7C1062GE devices are available in Pb-free

119-ball plastic ball grid array (PBGA) package.

For a complete list of related documentation, click here.

Note

1. This device does not support automatic write-back on error detection.

Cypress Semiconductor Corporation

Document Number: 001-81609 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 30, 2017

12 3 4 5 6 7...20

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与CY7C1062GE30-10BGXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1062GE30-10BGXIT	CYPRESS	获取价格	16-Mbit (512 K words Ã 32 bits) Static RAM w
CY7C1062GE30-10BGXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1062GN30-10BGXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1062GN30-10BGXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C106-35DC	ETC	获取价格	x4 SRAM
CY7C106-35DMB	ETC	获取价格	x4 SRAM
CY7C106-35LC	ETC	获取价格	x4 SRAM
CY7C106-35LMB	ETC	获取价格	x4 SRAM
CY7C106-35PC	ETC	获取价格	x4 SRAM
CY7C106-35VC	ETC	获取价格	x4 SRAM

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