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CY7C1062AV33-12BGI PDF预览

CY7C1062AV33-12BGI

更新时间: 2024-11-25 21:54:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
9页 191K
描述
The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits.

CY7C1062AV33-12BGI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数:119Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.84Is Samacsys:N
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:16777216 bit
内存集成电路类型:STANDARD SRAM内存宽度:32
湿度敏感等级:3功能数量:1
端子数量:119字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):220电源:3.3 V
认证状态:Not Qualified座面最大高度:2.4 mm
最大待机电流:0.05 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.26 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

CY7C1062AV33-12BGI 数据手册

 浏览型号CY7C1062AV33-12BGI的Datasheet PDF文件第2页浏览型号CY7C1062AV33-12BGI的Datasheet PDF文件第3页浏览型号CY7C1062AV33-12BGI的Datasheet PDF文件第4页浏览型号CY7C1062AV33-12BGI的Datasheet PDF文件第5页浏览型号CY7C1062AV33-12BGI的Datasheet PDF文件第6页浏览型号CY7C1062AV33-12BGI的Datasheet PDF文件第7页 
CY7C1062AV33  
512K x 32 Static RAM  
the address pins (A0 through A18). If Byte Enable B (BB) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A18).  
Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23  
and I/O24 to I/O31, respectively.  
Features  
• High speed  
— tAA = 8, 10, 12 ns  
• Low active power  
Reading from the device is accomplished by enabling the chip  
(CE1, CE2, and CE3 LOW) while forcing the Output Enable  
(OE) LOW and Write Enable (WE) HIGH. If the first Byte  
Enable (BA) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
Enable B (BB) is LOW, then data from memory will appear on  
I/O8 to I/O15. Similarly, Bc and BD correspond to the third and  
fourth bytes. See the truth table at the back of this data sheet  
for a complete description of read and write modes.  
— 1080 mW (max.)  
• Operating voltages of 3.3 ± 0.3V  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and CE3  
features  
Functional Description  
The input/output pins (I/O0 through I/O31) are placed in a  
high-impedance state when the device is deselected (CE1,  
CE2or CE3 HIGH), the outputs are disabled (OE HIGH), the  
byte selects are disabled (BA-D HIGH), or during a write  
operation (CE1, CE2, and CE3 LOW, and WE LOW).  
The CY7C1062AV33 is a high-performance CMOS Static  
RAM organized as 524,288 words by 32 bits.  
Writing to the device is accomplished by enabling the chip  
(CE1, CE2 and CE3 LOW) and forcing the Write Enable (WE)  
input LOW. If Byte Enable A (BA) is LOW, then data from I/O  
pins (I/O0 through I/O7), is written into the location specified on  
The CY7C1062AV33 is available in a 119-ball pitch ball grid  
array (PBGA) package.  
WE  
CE1  
CE2  
Logic Block Diagram  
CE3  
INPUT BUFFERS  
OE  
BA  
BB  
BC  
A
A
A
A
A
0
1
2
3
4
BD  
512K x 32  
ARRAY  
I/O0I/O31  
A
A
5
6
4096 x 4096  
A
A
A
7
8
9
COLUMN  
DECODER  
Selection Guide  
–8  
8
–10  
10  
–12  
12  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Coml  
300  
300  
50  
275  
275  
50  
260  
260  
50  
mA  
Indl  
Maximum CMOS Standby Current  
Coml/Indl  
mA  
Cypress Semiconductor Corporation  
Document #: 38-05137 Rev. *D  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised February 21, 2003  

CY7C1062AV33-12BGI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1062AV33-12BGC CYPRESS

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