Datasheet > CY7C1049D_11

CY7C1049D_11

更新时间： 2024-11-09 09:43:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	317K
描述
4-Mbit (512 K × 8) Static RAM TTL-compatible inputs and outputs

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CY7C1049D_11 数据手册

CY7C1049D

4-Mbit (512 K × 8) Static RAM

Features

Functional Description^[1]

■ Pin- and function-compatible with CY7C1049B

The CY7C1049D is a high-performance CMOS static RAM

organized as 512K words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (CE), an active

LOW Output Enable (OE), and tri-state drivers. Writing to the

device is accomplished by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. Data on the eight I/O pins (I/O₀

through I/O₇) is then written into the location specified on the

address pins (A₀through A₁₈).

■ High speed

❐ t_AA= 10 ns

■ Low active power

❐ I_CC= 90 mA at 10 ns

■ Low CMOS Standby power

❐ I_SB2= 10 mA

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

■ 2.0 V data retention

■ Automatic power-down when deselected

■ TTL-compatible inputs and outputs

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

■ Easy memory expansion with CE and OE features

■ Available in Pb-free 36-Pin (400-Mil) Molded SOJ package

The CY7C1049D is available in a standard 400-mil-wide

36-pin SOJ package with center power and ground (revolu-

tionary) pinout.

Logic Block Diagram

I/O₀

INPUT BUFFER

A₀

A₁

A₂

A₃

A₄

A₅

A₆

A₇

A₈

A₉

I/O₁

I/O₂

I/O₃

I/O₄

I/O₅

512K x 8

A₁₀

I/O₆

POWER

DOWN

COLUMN

DECODER

I/O₇

Selection Guide

–10

Unit

Maximum access time

Maximum operating current

Maximum CMOS standby current

Note

1. For guidelines on SRAM system design, refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05474 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 20, 2011

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与CY7C1049D_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1049D-10VXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY7C1049D-15VXC	CYPRESS	获取价格	Standard SRAM, 512KX8, 15ns, CMOS, PDSO36, 0.400 INCH, LEAD FREE, SOJ-36
CY7C1049DV33	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY7C1049DV33_07	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY7C1049DV33_11	CYPRESS	获取价格	4-Mbit (512 K x 8) Static RAM Automatic power down when deselected
CY7C1049DV33-10VXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY7C1049DV33-10VXI	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 10ns, PDSO36, 0.400 INCH, LEAD FREE, SOJ-36
CY7C1049DV33-10VXIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 10ns, CMOS, PDSO36, 0.400 INCH, LEAD FREE, PLASTIC, SOJ-36
CY7C1049DV33-10ZSXC	CYPRESS	获取价格	Standard SRAM, 512KX8, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1049DV33-10ZSXI	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 10ns, PDSO44, LEAD FREE, TSOP2-44

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