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CY7C1049BNV33-15VXI PDF预览

CY7C1049BNV33-15VXI

更新时间: 2024-09-17 03:22:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
8页 420K
描述
512K x 8 Static RAM

CY7C1049BNV33-15VXI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.400 INCH, LEAD FREE, SOJ-36
针数:36Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.14Is Samacsys:N
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J36JESD-609代码:e4
长度:23.495 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:36字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ36,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
座面最大高度:3.683 mm最大待机电流:0.008 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.2 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

CY7C1049BNV33-15VXI 数据手册

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CY7C1049BNV33  
512K x 8 Static RAM  
Features  
Functional Description[1]  
• High speed  
The CY7C1049BNV33 is a high-performance CMOS Static  
RAM organized as 524,288 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and three-state drivers.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location  
specified on the address pins (A0 through A18).  
— tAA = 12 ns  
• Low active power  
— 504 mW (max.)  
• Low CMOS standby power (Commercial L version)  
— 1.8 mW (max.)  
2.0V Data Retention (660 µW at 2.0V retention)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1049BNV33 is available in a standard 400-mil-wide  
36-pin SOJ and 44-pin TSOPII packages with center power  
and ground (revolutionary) pinout.  
Logic Block Diagram  
Pin Configuration  
TSOP  
SOJ  
Top View  
Top View  
A
A
36  
35  
34  
33  
1
2
3
4
5
6
7
8
9
44  
NC  
NC  
NC  
1
0
1
NC  
NC  
43  
42  
41  
40  
39  
38  
2
3
4
5
6
A
A
A
A
18  
17  
16  
15  
NC  
A
0
A
2
A
A
1
18  
A
A
3
4
A
A
2
17  
32  
I/O0  
A
A
16  
3
INPUTBUFFER  
CE  
31  
30  
29  
28  
OE  
I/O  
A
A
4
CE  
7
15  
A0  
A1  
A2  
A3  
A4  
37  
36  
35  
34  
33  
I/O1  
I/O2  
I/O  
8
OE  
I/O  
0
1
7
I/O  
9
0
I/O  
I/O  
V
7
6
10  
11  
12  
13  
I/O  
V
SS  
I/O  
1
CC  
6
GND  
CC  
V
SS  
27  
26  
25  
GND  
I/O  
I/O3  
10  
11  
12  
13  
A5  
A6  
A7  
A8  
A9  
V
I/O3  
I/O4  
I/O5  
CC  
V
V
512K x 8  
ARRAY  
CC  
I/O  
32  
I/O  
I/O  
5
2
2
5
4
I/O  
31  
30  
29  
28  
I/O  
A
I/O  
14  
15  
16  
17  
18  
19  
20  
4
3
WE  
WE  
14  
24  
23  
22  
21  
20  
19  
A
14  
A10  
A
A
13  
5
A
A
A
A
A
14  
15  
16  
17  
18  
13  
5
A
12  
A
6
A
A
12  
A
6
I/O6  
I/O7  
27  
26  
25  
11  
7
POWER  
DOWN  
COLUMN  
A
A
CE  
A
10  
NC  
7
11  
8
9
DECODER  
A
A
8
10  
WE  
NC  
NC  
NC 21  
24  
23  
A
NC  
9
22  
NC  
OE  
Cypress Semiconductor Corporation  
Document #: 001-06432 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 1, 2006  
[+] Feedback  

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