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CY7C1049BV33-17ZI PDF预览

CY7C1049BV33-17ZI

更新时间: 2024-09-16 22:09:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 167K
描述
512K x 8 Static RAM

CY7C1049BV33-17ZI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP44,.46,32针数:44
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.72
最长访问时间:17 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e0
长度:18.41 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.008 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.18 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY7C1049BV33-17ZI 数据手册

 浏览型号CY7C1049BV33-17ZI的Datasheet PDF文件第2页浏览型号CY7C1049BV33-17ZI的Datasheet PDF文件第3页浏览型号CY7C1049BV33-17ZI的Datasheet PDF文件第4页浏览型号CY7C1049BV33-17ZI的Datasheet PDF文件第5页浏览型号CY7C1049BV33-17ZI的Datasheet PDF文件第6页浏览型号CY7C1049BV33-17ZI的Datasheet PDF文件第7页 
049BV33  
CY7C1049BV33  
512K x 8 Static RAM  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and three-state drivers. Writ-  
ing to the device is accomplished by taking Chip Enable (CE)  
and Write Enable (WE) inputs LOW. Data on the eight I/O pins  
(I/O0 through I/O7) is then written into the location specified on  
the address pins (A0 through A18).  
Features  
• High speed  
— tAA = 15 ns  
• Low active power  
— 504 mW (max.)  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• Low CMOS standby power (Commercial L version)  
— 1.8 mW (max.)  
2.0V Data Retention (660 µW at 2.0V retention)  
Automatic power-down when deselected  
TTL-compatible inputs and outputs  
Easy memory expansion with CE and OE features  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description[1]  
The CY7C1049BV33 is available in a standard 400-mil-wide  
36-pin SOJ and 44-pin TSOPII packages with center power  
and ground (revolutionary) pinout.  
The CY7C1049BV33 is a high-performance CMOS Static  
RAM organized as 524,288 words by 8 bits. Easy memory  
Logic Block Diagram  
Pin Configuration  
SOJ  
TSOP II  
Top View  
Top View  
A
A
36  
35  
34  
33  
1
2
3
4
5
6
7
8
9
44  
NC  
NC  
NC  
1
0
1
NC  
NC  
43  
42  
41  
40  
39  
38  
2
3
4
5
6
A
A
A
A
18  
17  
16  
15  
NC  
A
0
A
2
A
A18  
1
A
A
3
4
A
17  
A
2
32  
I/O0  
A
16  
A
3
INPUT BUFFER  
CE  
31  
30  
29  
28  
OE  
I/O  
A
15  
A
7
4
A0  
A1  
A2  
A3  
A4  
37  
36  
35  
34  
33  
I/O1  
I/O  
CE  
OE  
I/O  
8
0
1
7
I/O  
9
0
I/O  
I/O  
V
7
6
I/O2  
10  
11  
12  
I/O  
V
SS  
I/O  
1
CC  
6
GND  
CC  
V
SS  
27  
26  
25  
GND  
I/O  
I/O3  
10  
11  
12  
13  
A5  
V
I/O3  
I/O4  
I/O5  
CC  
V
V
512K x 8  
ARRAY  
CC  
A6  
I/O  
32  
I/O  
I/O  
2
5
13  
14  
2
5
4
A7  
A8  
A9  
I/O  
I/O  
A
31  
30  
29  
28  
I/O  
4
3
WE 15  
WE  
24  
23  
22  
21  
20  
19  
14  
A
14  
A10  
A
A
A
16  
17  
18  
19  
20  
A
13  
12  
11  
5
A
A
A
A
A
14  
15  
16  
17  
18  
13  
5
A
6
A
A
12  
6
27  
26  
25  
I/O6  
I/O7  
7
POWER  
DOWN  
COLUMN  
DECODER  
A
A
CE  
A
7
11  
10  
8
9
A
NC  
NC  
NC  
A
8
10  
WE  
NC 21  
24  
23  
A
NC  
9
22  
NC  
OE  
Selection Guide  
-12  
-15  
-17  
17  
-20  
-25  
Maximum Access Time (ns)  
12  
15  
180  
200  
8
20  
25  
150  
170  
8
Maximum Operating Current (mA) Comml  
Indl  
200  
220  
8
170  
180  
8
160  
170  
8
Maximum CMOS Standby  
Current (mA)  
Coml/Indl  
Coml  
L
0.5  
0.5  
0.5  
0.5  
0.5  
Note:  
1. For guidelines on SRAM system design, please refer to the System Design GuidelinesCypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05139 Rev. *A  
Revised September 13, 2002  

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