5秒后页面跳转
CY7C1049CV33_1106 PDF预览

CY7C1049CV33_1106

更新时间: 2024-11-07 09:43:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 286K
描述
4-Mbit (512 K × 8) Static RAM Automatic power down when deselected

CY7C1049CV33_1106 数据手册

 浏览型号CY7C1049CV33_1106的Datasheet PDF文件第2页浏览型号CY7C1049CV33_1106的Datasheet PDF文件第3页浏览型号CY7C1049CV33_1106的Datasheet PDF文件第4页浏览型号CY7C1049CV33_1106的Datasheet PDF文件第5页浏览型号CY7C1049CV33_1106的Datasheet PDF文件第6页浏览型号CY7C1049CV33_1106的Datasheet PDF文件第7页 
CY7C1049CV33  
4-Mbit (512 K × 8) Static RAM  
4-Mbit (512  
K × 8) Static RAM  
Features  
Functional Description  
Temperature ranges  
Commercial: 0 °C to 70 °C  
Industrial: –40 °C to 85 °C  
The CY7C1049CV33 is a high performance Complementary  
metal oxide semiconductor (CMOS) Static RAM organized as  
524,288 words by eight bits. Easy memory expansion is provided  
by an active LOW Chip Enable (CE), an active LOW Output  
Enable (OE), and three-state drivers. Writing to the device is  
accomplished by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A18).  
High speed  
tAA = 8 ns  
Low active power  
360 mW (max)  
2.0 V data retention  
Reading from the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
Automatic power down when deselected  
Transistor- transistor logic (TTL) compatible inputs and outputs  
Easy memory expansion with CE and OE features  
The eight input and output pins (I/O0 through I/O7) are placed in  
a high impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1049CV33 is available in standard 44-pin TSOP II  
package with center power and ground (revolutionary) pinout.  
Logic Block Diagram  
A
0
IO  
0
INPUT BUFFER  
A
1
A
2
IO  
1
A
3
A
4
IO  
2
A
5
A
6
512K x 8  
ARRAY  
IO  
3
A
A
A
A
A
A
7
8
IO  
4
9
10  
11  
12  
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 38-05006 Rev. *M  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 14, 2011  
[+] Feedback  

与CY7C1049CV33_1106相关器件

型号 品牌 获取价格 描述 数据表
CY7C1049CV33-10VC ROCHESTER

获取价格

Standard SRAM
CY7C1049CV33-10VC CYPRESS

获取价格

512K x 8 Static RAM
CY7C1049CV33-10VCT CYPRESS

获取价格

Standard SRAM, 512KX8, 10ns, CMOS, PDSO36, 0.400 INCH, SOJ-36
CY7C1049CV33-10VI CYPRESS

获取价格

512K x 8 Static RAM
CY7C1049CV33-10VIT CYPRESS

获取价格

Standard SRAM, 512KX8, 10ns, CMOS, PDSO36, 0.400 INCH, SOJ-36
CY7C1049CV33-10VXA CYPRESS

获取价格

4 Mbit (512K x 8) Static RAM
CY7C1049CV33-10VXAT CYPRESS

获取价格

Standard SRAM, 512KX8, 10ns, CMOS, PDSO36, 0.400 INCH, LEAD FREE, SOJ-36
CY7C1049CV33-10VXC CYPRESS

获取价格

4-Mbit (512K x 8) Static RAM
CY7C1049CV33-10VXCT CYPRESS

获取价格

Standard SRAM, 512KX8, 10ns, CMOS, PDSO36,
CY7C1049CV33-10VXI CYPRESS

获取价格

4-Mbit (512K x 8) Static RAM