Datasheet > CY7C1049CV33_10

CY7C1049CV33_10

更新时间： 2024-11-07 06:51:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	886K
描述
4 Mbit (512K x 8) Static RAM

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CY7C1049CV33_10 数据手册

CY7C1049CV33

4 Mbit (512K x 8) Static RAM

Features

Functional Description

■ Temperature ranges

❐ Commercial: 0°C to 70°C

❐ Industrial/Automotive -A: –40°C to 85°C

❐ Automotive-E: –40°C to 125°C

The CY7C1049CV33 is a high performance CMOS Static RAM

organized as 524,288 words by eight bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and three-state drivers. Writing

to the device is accomplished by taking Chip Enable (CE) and

Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O₀

through I/O₇) is then written into the location specified on the

address pins (A₀through A₁₈).

■ High Speed

❐ t_AA= 10 ns

■ Low Active Power

❐ 324 mW (max)

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ 2.0V Data Retention

■ Automatic Power Down when Deselected

■ TTL-compatible Inputs and Outputs

■ Easy Memory Expansion with CE and OE features

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

The CY7C1049CV33 is available in standard 400-mil-wide

36-pin SOJ package and 44-pin TSOP II package with center

power and ground (revolutionary) pinout.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

INPUT BUFFER

512K x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Cypress Semiconductor Corporation

Document #: 38-05006 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•408-943-2600

Revised January 07, 2010

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