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CY7C1049BN-25VI PDF预览

CY7C1049BN-25VI

更新时间: 2024-09-17 05:19:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 454K
描述
512K x 8 Static RAM

CY7C1049BN-25VI 数据手册

 浏览型号CY7C1049BN-25VI的Datasheet PDF文件第2页浏览型号CY7C1049BN-25VI的Datasheet PDF文件第3页浏览型号CY7C1049BN-25VI的Datasheet PDF文件第4页浏览型号CY7C1049BN-25VI的Datasheet PDF文件第5页浏览型号CY7C1049BN-25VI的Datasheet PDF文件第6页浏览型号CY7C1049BN-25VI的Datasheet PDF文件第7页 
1CY7C1049BN  
CY7C1049BN  
512K x 8 Static RAM  
Features  
Functional Description[1]  
• High speed  
The CY7C1049BN is a high-performance CMOS static RAM  
organized as 524,288 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and three-state drivers.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location  
specified on the address pins (A0 through A18).  
— tAA = 12 ns  
• Low active power  
— 1320 mW (max.)  
• Low CMOS standby power (Commercial L version)  
— 2.75 mW (max.)  
• 2.0V Data Retention (400 µW at 2.0V retention)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1049BN is available in a standard 400-mil-wide  
36-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
36  
35  
34  
33  
32  
1
NC  
0
1
2
3
4
A
A
A
A
18  
17  
16  
15  
A
2
A
A
3
4
5
CE  
31  
30  
29  
28  
6
OE  
I/O  
I/O  
7
8
9
0
1
7
I/O  
I/O  
V
I/O  
6
0
GND  
INPUT BUFFER  
CC  
27  
26  
25  
GND  
10  
11  
12  
13  
V
CC  
A
1
0
A
I/O  
I/O  
I/O  
I/O  
A
A
A
A
A
I/O  
1
5
4
2
I/O3  
WE  
A
2
24  
23  
22  
21  
20  
19  
14  
2
A
A
5
3
14  
15  
16  
17  
18  
13  
A
A
4
12  
6
A
7
A
11  
10  
5
I/O  
I/O  
I/O  
3
4
5
512K x 8  
ARRAY  
A
A
8
6
A
9
NC  
A
7
A
8
A
9
A
10  
I/O  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 001-06501 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 2, 2006  
[+] Feedback  

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