Datasheet > CY7C1021BNV33_11

CY7C1021BNV33_11

更新时间： 2024-11-23 09:43:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	547K
描述
64 K × 16 Static RAM CMOS for optimum speed/power

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CY7C1021BNV33_11 数据手册

CY7C1021BNV33

64 K × 16 Static RAM

K × 16 Static RAM

Features

Functional Description^[1]

■ 3.3 V operation (3.0 V–3.6 V)

The CY7C1021BNV33 is a high-performance CMOS static RAM

organized as 65,536 words by 16 bits. This device has an

automatic power-down feature that significantly reduces power

consumption when deselected.

■ High speed

❐ t_AA= 15 ns

■ CMOS for optimum speed/power

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is

LOW, then data from I/O pins (I/O₀through I/O₇), is written into

the location specified on the address pins (A₀through A₁₅). If

Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₈

through I/O₁₅) is written into the location specified on the address

pins (A₀through A₁₅).

■ Low Active Power

❐ 576 mW (max)

■ Low CMOS Standby Power

❐ 1.80 mW (max)

■ Automatic power-down when deselected

■ Independent control of upper and lower bits

■ Available in 44-pin TSOP II and 400-mil SOJ

■ Available in a 48-ball Mini BGA package

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins will

appear on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then

data from memory will appear on I/O₈to I/O₁₅. See the truth table

at the back of this data sheet for a complete description of read

and write modes.

The input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or during a write operation (CE LOW,

and WE LOW).

The CY7C1021BNV33 is available in 400-mil-wide SOJ,

standard 44-pin TSOP Type II, and 48-ball mini BGA packages.

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-06433 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 8, 2011

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与CY7C1021BNV33_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021BNV33L-10VXC	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021BNV33L-10VXCT	CYPRESS	获取价格	暂无描述
CY7C1021BNV33L-10ZXC	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021BNV33L-10ZXCT	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1021BNV33L-12ZC	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021BNV33L-12ZCT	CYPRESS	获取价格	Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, TSOP2-44
CY7C1021BNV33L-12ZXC	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021BNV33L-12ZXCT	CYPRESS	获取价格	Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1021BNV33L-15BAI	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021BNV33L-15BAIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PBGA48,

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