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CY7C1021BNV33L-15BAIT PDF预览

CY7C1021BNV33L-15BAIT

更新时间: 2024-11-23 19:56:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
17页 405K
描述
Standard SRAM, 64KX16, 15ns, CMOS, PBGA48,

CY7C1021BNV33L-15BAIT 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:MINIBGA-48
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.82
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:S-PBGA-B48长度:7 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:48字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,30封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.0001 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.16 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:7 mmBase Number Matches:1

CY7C1021BNV33L-15BAIT 数据手册

 浏览型号CY7C1021BNV33L-15BAIT的Datasheet PDF文件第2页浏览型号CY7C1021BNV33L-15BAIT的Datasheet PDF文件第3页浏览型号CY7C1021BNV33L-15BAIT的Datasheet PDF文件第4页浏览型号CY7C1021BNV33L-15BAIT的Datasheet PDF文件第5页浏览型号CY7C1021BNV33L-15BAIT的Datasheet PDF文件第6页浏览型号CY7C1021BNV33L-15BAIT的Datasheet PDF文件第7页 
CY7C1021BNV33  
64K × 16 Static RAM  
64K  
× 16 Static RAM  
Features  
Functional Description  
3.3 V operation (3.0 V–3.6 V)  
The CY7C1021BNV33[1] is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has an  
automatic power-down feature that significantly reduces power  
consumption when deselected.  
High speed  
tAA = 15 ns  
CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable (CE)  
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is  
LOW, then data from I/O pins (I/O0 through I/O7), is written into  
the location specified on the address pins (A0 through A15). If  
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8  
through I/O15) is written into the location specified on the address  
pins (A0 through A15).  
Low Active Power  
576 mW (max)  
Low CMOS Standby Power  
1.80 mW (max)  
Automatic power-down when deselected  
Reading from the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins will  
appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then  
data from memory will appear on I/O8 to I/O15. See the truth table  
at the back of this data sheet for a complete description of read  
and write modes.  
Independent control of upper and lower bits  
Available in 44-pin TSOP II and 48-ball Mini BGA package  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE HIGH),  
the outputs are disabled (OE HIGH), the BHE and BLE are  
disabled (BHE, BLE HIGH), or during a write operation (CE LOW,  
and WE LOW).  
The CY7C1021BNV33 is available in standard 44-pin TSOP  
Type II and 48-ball mini BGA packages.  
For a complete list of related documentation, click here.  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 001-06433 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 13, 2017  
 
 

CY7C1021BNV33L-15BAIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1021BNV33L-15BAI CYPRESS

完全替代

64K x 16 Static RAM

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