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CY7C1021BV33-12BAC PDF预览

CY7C1021BV33-12BAC

更新时间： 2024-11-25 22:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 242K
描述
64K x 16 Static RAM

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中文翻译

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CY7C1021BV33-12BAC 数据手册

 浏览型号CY7C1021BV33-12BAC的Datasheet PDF文件第2页浏览型号CY7C1021BV33-12BAC的Datasheet PDF文件第3页浏览型号CY7C1021BV33-12BAC的Datasheet PDF文件第4页浏览型号CY7C1021BV33-12BAC的Datasheet PDF文件第5页浏览型号CY7C1021BV33-12BAC的Datasheet PDF文件第6页浏览型号CY7C1021BV33-12BAC的Datasheet PDF文件第7页 
021BV33  
CY7C1021BV33  
64K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• 3.3V operation (3.0V–3.6V)  
• High speed  
— tAA = 10/12/15 ns  
• CMOS for optimum speed/power  
• Low Active Power (L version)  
— 576 mW (max.)  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O9 to I/O16. See the  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
• Low CMOS Standby Power (L version)  
— 1.80 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in 44-pin TSOP II and 400-mil SOJ  
• Available in a 48-Ball Mini BGA package  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected  
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and  
BLE are disabled (BHE, BLE HIGH), or during a write opera-  
tion (CE LOW, and WE LOW).  
Functional Description[1]  
The CY7C1021BV is a high-performance CMOS static RAM  
organized as 65,536 words by 16 bits. This device has an au-  
tomatic power-down feature that significantly reduces power  
consumption when deselected.  
The CY7C1021BV is available in 400-mil-wide SOJ, standard  
44-pin TSOP Type II, and 48-ball mini BGA packages.  
Logic Block Diagram  
Pin Configurations  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
1
A
A
A
A
A
A
5
4
3
2
1
0
43  
42  
41  
40  
39  
38  
A
2
3
4
5
6
6
A
7
A
A
A
7
6
5
4
OE  
BHE  
BLE  
I/O  
I/O  
I/O  
64K x 16  
CE  
A
A
A
A
I/O –I/O  
RAM Array  
512 X 2048  
I/O  
1
8
7
1
16  
37  
36  
35  
34  
33  
3
2
I/O  
I/O  
8
2
3
15  
14  
13  
I/O –I/O  
9
9
16  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
1
0
4
CC  
V
SS  
A
V
V
I/O  
I/O  
CC  
32  
I/O  
5
6
7
8
12  
11  
10  
9
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
BHE  
19  
A
A
14  
9
10  
11  
WE  
CE  
OE  
A
20  
21  
22  
A
A
13  
A
12  
24  
23  
NC  
NC  
BLE  
Selection Guide  
7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15  
Maximum Access Time (ns)  
Maximum Operating Current (mA) Commercial  
Industrial  
8
170  
190  
5
10  
160  
180  
5
12  
150  
170  
5
15  
140  
160  
5
Maximum CMOS Standby Current Commercial  
(mA)  
L
0.500  
0.500  
0.500  
0.500  
Shaded areas contain advance information.  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05148 Rev. *A  
Revised September 13, 2002  
1234567...11

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