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CY7C1021BV33-10ZC PDF预览

CY7C1021BV33-10ZC

更新时间： 2024-11-22 22:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
11页 242K
描述
64K x 16 Static RAM

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中文翻译

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CY7C1021BV33-10ZC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2-44
针数：44Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.04最长访问时间：10 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e0长度：18.41 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.005 A
最小待机电流：3 V子类别：SRAMs
最大压摆率：0.21 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：2.97 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：10.16 mmBase Number Matches：1

CY7C1021BV33-10ZC 数据手册

 浏览型号CY7C1021BV33-10ZC的Datasheet PDF文件第2页浏览型号CY7C1021BV33-10ZC的Datasheet PDF文件第3页浏览型号CY7C1021BV33-10ZC的Datasheet PDF文件第4页浏览型号CY7C1021BV33-10ZC的Datasheet PDF文件第5页浏览型号CY7C1021BV33-10ZC的Datasheet PDF文件第6页浏览型号CY7C1021BV33-10ZC的Datasheet PDF文件第7页 
021BV33  
CY7C1021BV33  
64K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• 3.3V operation (3.0V–3.6V)  
• High speed  
— tAA = 10/12/15 ns  
• CMOS for optimum speed/power  
• Low Active Power (L version)  
— 576 mW (max.)  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O9 to I/O16. See the  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
• Low CMOS Standby Power (L version)  
— 1.80 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in 44-pin TSOP II and 400-mil SOJ  
• Available in a 48-Ball Mini BGA package  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected  
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and  
BLE are disabled (BHE, BLE HIGH), or during a write opera-  
tion (CE LOW, and WE LOW).  
Functional Description[1]  
The CY7C1021BV is a high-performance CMOS static RAM  
organized as 65,536 words by 16 bits. This device has an au-  
tomatic power-down feature that significantly reduces power  
consumption when deselected.  
The CY7C1021BV is available in 400-mil-wide SOJ, standard  
44-pin TSOP Type II, and 48-ball mini BGA packages.  
Logic Block Diagram  
Pin Configurations  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
1
A
A
A
A
A
A
5
4
3
2
1
0
43  
42  
41  
40  
39  
38  
A
2
3
4
5
6
6
A
7
A
A
A
7
6
5
4
OE  
BHE  
BLE  
I/O  
I/O  
I/O  
64K x 16  
CE  
A
A
A
A
I/O –I/O  
RAM Array  
512 X 2048  
I/O  
1
8
7
1
16  
37  
36  
35  
34  
33  
3
2
I/O  
I/O  
8
2
3
15  
14  
13  
I/O –I/O  
9
9
16  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
1
0
4
CC  
V
SS  
A
V
V
I/O  
I/O  
CC  
32  
I/O  
5
6
7
8
12  
11  
10  
9
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
BHE  
19  
A
A
14  
9
10  
11  
WE  
CE  
OE  
A
20  
21  
22  
A
A
13  
A
12  
24  
23  
NC  
NC  
BLE  
Selection Guide  
7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15  
Maximum Access Time (ns)  
Maximum Operating Current (mA) Commercial  
Industrial  
8
170  
190  
5
10  
160  
180  
5
12  
150  
170  
5
15  
140  
160  
5
Maximum CMOS Standby Current Commercial  
(mA)  
L
0.500  
0.500  
0.500  
0.500  
Shaded areas contain advance information.  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05148 Rev. *A  
Revised September 13, 2002  
1234567...11

中文翻译

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CY7C1021BV33-10ZCT CYPRESS

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CY7C1021BV33-12BAC CYPRESS

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 		64K x 16 Static RAM
CY7C1021BV33-12BACT CYPRESS

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CY7C1021BV33-12BAI CYPRESS

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CY7C1021BV33-12BAIT CYPRESS

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CY7C1021BV33-12VC CYPRESS

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 		64K x 16 Static RAM
CY7C1021BV33-12VI ROCHESTER

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 		Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44
CY7C1021BV33-12VI CYPRESS

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 		64K x 16 Static RAM
CY7C1021BV33-12ZC CYPRESS

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 		64K x 16 Static RAM
CY7C1021BV33-12ZCT CYPRESS

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 		Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, TSOP2-44

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