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CY7C1021BNV33L-10VXCT

更新时间： 2024-11-23 13:02:07
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赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
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CY7C1021BNV33L-10VXCT 数据手册

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CY7C1021BNV33  
64K x 16 Static RAM  
Features  
Functional Description[1]  
• 3.3V operation (3.0V–3.6V)  
The CY7C1021BNV is a high-performance CMOS static RAM  
organized as 65,536 words by 16 bits. This device has an  
automatic power-down feature that significantly reduces  
power consumption when deselected.  
• High speed  
— tAA = 10, 12, 15 ns  
• CMOS for optimum speed/power  
• Low Active Power (L version)  
— 576 mW (max.)  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
• Low CMOS Standby Power (L version)  
— 1.80 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in 44-pin TSOP II and 400-mil SOJ  
• Available in a 48-Ball Mini BGA package  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected  
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and  
BLE are disabled (BHE, BLE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1021BNV is available in 400-mil-wide SOJ,  
standard 44-pin TSOP Type II, and 48-ball mini BGA  
packages.  
Logic Block Diagram  
Pin Configurations  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
1
A
A
5
4
43  
42  
41  
40  
39  
38  
A
A
6
2
3
4
5
6
3
A
A
2
7
A7  
A6  
OE  
A
1
BHE  
BLE  
I/O  
A
0
A5  
A4  
A3  
A2  
64K x 16  
CE  
I/O1–I/O8  
RAM Array  
512 X 2048  
I/O  
7
1
16  
37  
36  
35  
34  
33  
I/O  
I/O  
8
I/O  
I/O  
I/O  
2
3
15  
14  
13  
I/O9–I/O16  
9
A1  
A0  
10  
11  
12  
13  
I/O  
4
VSS  
VCC  
VSS  
VCC  
I/O  
I/O  
I/O  
I/O  
32  
I/O  
5
12  
11  
10  
9
31  
30  
29  
28  
I/O  
6
14  
15  
16  
I/O  
7
COLUMN DECODER  
I/O  
8
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
BHE  
19  
A
A
14  
9
WE  
CE  
OE  
A
A
12  
NC  
20  
21  
22  
A
11  
NC  
13  
10  
A
24  
23  
BLE  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com  
Cypress Semiconductor Corporation  
Document #: 001-06433 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 1, 2006  
1234567...10

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