Datasheet > CY7C1020CV33_10

CY7C1020CV33_10

更新时间： 2024-01-22 04:53:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	446K
描述
512 K (32 K × 16) Static RAM

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中文翻译

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CY7C1020CV33_10 数据手册

CY7C1020CV33

512 K (32 K × 16) Static RAM

512

K (32 K × 16) Static RAM

Features

Functional Description

■ Pin- and function-compatible with CY7C1020CV33

The CY7C1020CV33 is a high-performance CMOS static RAM

organized as 32,768 words by 16 bits. This device has an

automatic power-down feature that significantly reduces power

consumption when deselected.

■ Temperature Ranges

❐ Commercial: 0 °C to 70 °C

❐ Industrial: –40 °C to 85 °C

❐ Automotive: –40 °C to 125 °C

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is

LOW, then data from I/O pins (I/O₁through I/O₈), is written into

the location specified on the address pins (A₀through A₁₄). If

Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₉

through I/O₁₆) is written into the location specified on the address

pins (A₀through A₁₄).

■ High speed

❐ t_AA= 10 ns

■ CMOS for optimum speed/power

■ Low active power

❐ 325 mW (max)

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins will

appear on I/O₁to I/O₈. If Byte High Enable (BHE) is LOW, then

data from memory will appear on I/O₉to I/O₁₆. See the truth table

at the back of this data sheet for a complete description of read

and write modes.

■ Automatic power-down when deselected

■ Independent control of upper and lower bits

■ Available in Pb-free and non Pb-free 44-pin TSOP II package

The input/output pins (I/O₁through I/O₁₆) are placed in a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or during a write operation (CE LOW,

and WE LOW).

The CY7C1020CV33 is available in standard 44-pin TSOP Type

II package.

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

A₄

A₃

A₂

32K × 16

I/O₁–I/O₈

RAM Array

I/O₉–I/O₁₆

A₁

A₀

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05133 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 2, 2010

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与CY7C1020CV33_10相关器件

型号	品牌	获取价格	描述	数据表
CY7C1020CV33_12	CYPRESS	获取价格	512 K (32 K Ã 16) Static RAM
CY7C1020CV33-10ZC	CYPRESS	获取价格	32K x 16 Static RAM
CY7C1020CV33-10ZCT	CYPRESS	获取价格	Standard SRAM, 32KX16, 10ns, CMOS, PDSO44, TSOP2-44
CY7C1020CV33-10ZI	CYPRESS	获取价格	32K x 16 Static RAM
CY7C1020CV33-10ZXC	CYPRESS	获取价格	512K (32K x 16) Static RAM
CY7C1020CV33-12ZC	CYPRESS	获取价格	32K x 16 Static RAM
CY7C1020CV33-12ZCT	CYPRESS	获取价格	Standard SRAM, 32KX16, 12ns, CMOS, PDSO44, TSOP2-44
CY7C1020CV33-12ZI	CYPRESS	获取价格	32K x 16 Static RAM
CY7C1020CV33-15ZC	CYPRESS	获取价格	32K x 16 Static RAM
CY7C1020CV33-15ZE	CYPRESS	获取价格	512K (32K x 16) Static RAM

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