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CY7C1020BL-12ZC PDF预览

CY7C1020BL-12ZC

更新时间: 2024-10-27 22:07:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
10页 183K
描述
32K x 16 Static RAM

CY7C1020BL-12ZC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2-44针数:44
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.6
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e0
长度:18.415 mm内存密度:524288 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.194 mm
最大待机电流:0.0005 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.14 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY7C1020BL-12ZC 数据手册

 浏览型号CY7C1020BL-12ZC的Datasheet PDF文件第2页浏览型号CY7C1020BL-12ZC的Datasheet PDF文件第3页浏览型号CY7C1020BL-12ZC的Datasheet PDF文件第4页浏览型号CY7C1020BL-12ZC的Datasheet PDF文件第5页浏览型号CY7C1020BL-12ZC的Datasheet PDF文件第6页浏览型号CY7C1020BL-12ZC的Datasheet PDF文件第7页 
020B  
CY7C1020B  
32K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• High speed  
— tAA = 12, 15 ns  
• CMOS for optimum speed/power  
• Low active power  
— 825 mW (max.)  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O9 to I/O16. See the  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
• Low CMOS standby power (L version only)  
— 2.75 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in 44-pin TSOP II and 400-mil SOJ  
Functional Description  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1020B is a high-performance CMOS static RAM or-  
ganized as 32,768 words by 16 bits. This device has an auto-  
matic power-down feature that significantly reduces power  
consumption when deselected.  
The CY7C1020B is available in standard 44-pin TSOP Type II  
and 400-mil-wide SOJ packages.  
Logic Block Diagram  
Pin Configuration  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
1
2
3
4
5
6
NC  
A
5
43  
42  
41  
40  
39  
38  
A
A
3
6
A
2
A
7
A
A
A
7
6
5
4
OE  
A
1
A
BHE  
BLE  
I/O  
0
32K x 16  
CE  
A
A
A
A
I/O –I/O  
RAM Array  
I/O  
1
8
7
1
16  
37  
36  
35  
34  
33  
3
2
I/O  
I/O  
8
I/O  
I/O  
2
3
15  
14  
13  
I/O I/O  
9
9
16  
10  
11  
12  
I/O  
V
SS  
I/O  
1
0
4
CC  
V
SS  
A
V
V
CC  
I/O  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
13  
5
6
7
8
12  
11  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
10  
9
COLUMN DECODER  
WE 17  
18  
NC  
A
A
A
A
15  
14  
13  
8
BHE  
19  
20  
21  
22  
26  
25  
A
9
10  
11  
WE  
CE  
OE  
A
A
A
12  
24  
23  
NC  
NC  
BLE  
Selection Guide  
7C1020B-12  
7C1020B-15  
Maximum Access Time (ns)  
Commercial  
Commercial  
Commercial  
L
12  
140  
3
15  
130  
3
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
0.5  
0.5  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05171 Rev. *A  
Revised August 20, 2002  

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