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CY7C1020BN-12VXC PDF预览

CY7C1020BN-12VXC

更新时间： 2024-02-13 09:28:30
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 416K
描述
32K x 16 Static RAM

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CY7C1020BN-12VXC 数据手册

 浏览型号CY7C1020BN-12VXC的Datasheet PDF文件第2页浏览型号CY7C1020BN-12VXC的Datasheet PDF文件第3页浏览型号CY7C1020BN-12VXC的Datasheet PDF文件第4页浏览型号CY7C1020BN-12VXC的Datasheet PDF文件第5页浏览型号CY7C1020BN-12VXC的Datasheet PDF文件第6页浏览型号CY7C1020BN-12VXC的Datasheet PDF文件第7页 
CY7C1020BN  
32K x 16 Static RAM  
Features  
Functional Description  
• High speed  
The CY7C1020BN is a high-performance CMOS static RAM  
organized as 32,768 words by 16 bits. This device has an  
automatic power-down feature that significantly reduces  
power consumption when deselected.  
— tAA = 12, 15 ns  
• CMOS for optimum speed/power  
• Low active power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
— 825 mW (max.)  
• Low CMOS standby power (L version only)  
— 2.75 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in 44-pin TSOP II and 400-mil SOJ  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1020BN is available in standard 44-pin TSOP Type  
II and 400-mil-wide SOJ packages.  
Logic Block Diagram  
Pin Configuration  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
1
NC  
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
A
2
7
A7  
A6  
A5  
A4  
A3  
A2  
OE  
A
1
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
32K x 16  
CE  
I/O1–I/O8  
RAM Array  
I/O  
7
1
16  
37  
36  
35  
34  
33  
I/O  
I/O  
8
2
3
15  
14  
13  
I/O9–I/O16  
9
A1  
A0  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
4
CC  
V
SS  
V
V
CC  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
I/O  
5
6
7
8
12  
11  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
10  
9
COLUMN DECODER  
WE 17  
NC  
18  
A
A
8
15  
BHE  
19  
26  
25  
A
A
14  
9
WE  
CE  
OE  
A
13  
20  
21  
22  
A
11  
10  
A
A
12  
24  
23  
NC  
NC  
BLE  
Cypress Semiconductor Corporation  
Document #: 001-06443 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised February 1, 2006  
[+] Feedback  
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CY7C1020BN-12VXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1020D-10VXI CYPRESS

完全替代

 512K (32K x 16) Static RAM

与CY7C1020BN-12VXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1020BN-12VXCT CYPRESS

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CY7C1020BN-12ZC CYPRESS

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 		32K x 16 Static RAM
CY7C1020BN-12ZCT CYPRESS

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 		Standard SRAM, 32KX16, 12ns, CMOS, PDSO44, TSOP2-44
CY7C1020BN-12ZXC CYPRESS

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 		32K x 16 Static RAM
CY7C1020BN-12ZXCT ROCHESTER

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 		32KX16 STANDARD SRAM, 12ns, PDSO44, LEAD FREE, TSOP2-44
CY7C1020BN-15ZC CYPRESS

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 		32K x 16 Static RAM
CY7C1020BN-15ZCT CYPRESS

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 		Standard SRAM, 32KX16, 15ns, CMOS, PDSO44, TSOP2-44
CY7C1020BN-15ZXC CYPRESS

获取价格

 		32K x 16 Static RAM
CY7C1020BN-15ZXC ROCHESTER

获取价格

 		32KX16 STANDARD SRAM, 15ns, PDSO44, LEAD FREE, TSOP2-44
CY7C1020BN-15ZXCT CYPRESS

获取价格

 		Standard SRAM, 32KX16, 15ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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