CY7C1020CV33
512K (32K x 16) Static RAM
Features
Functional Description
• Pin- and function-compatible with CY7C1020V33
• Temperature Ranges
The CY7C1020CV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
— tAA = 10 ns
• CMOS for optimum speed/power
• Low active power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
— 325 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin TSOP II
package
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020CV33 is available in standard 44-pin TSOP
Type II package.
PinConfiguration[1]
Logic Block Diagram
TSOP II
Top View
DATA IN DRIVERS
44
1
2
3
4
5
6
NC
A
5
43
42
41
40
39
38
A
A
3
6
A
A
2
7
A7
A6
OE
A
1
BHE
BLE
I/O
A
0
A5
A4
A3
A2
A1
A0
32K × 16
CE
I/O1–I/O8
RAM Array
I/O
7
1
16
37
36
35
34
33
I/O
I/O
8
I/O
I/O
2
3
15
14
13
I/O9–I/O16
9
10
11
12
13
I/O
V
SS
I/O
4
CC
V
SS
V
V
CC
32
31
30
29
28
27
I/O
I/O
I/O
5
6
7
8
12
11
I/O
I/O
I/O
14
15
16
I/O
10
9
COLUMN DECODER
I/O
WE 17
A4
NC
18
A
8
BHE
19
26
25
A
13
A
14
9
WE
CE
OE
A
20
21
22
A
11
10
A
A
12
24
23
NC
NC
BLE
Note:
1. NC pins are not connected on the die
Cypress Semiconductor Corporation
Document #: 38-05133 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
[+] Feedback