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CY7C1020B-15VCT PDF预览

CY7C1020B-15VCT

更新时间: 2024-10-28 21:20:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 490K
描述
Standard SRAM, 32KX16, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44

CY7C1020B-15VCT 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:44
Reach Compliance Code:unknownECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41Factory Lead Time:1 week
风险等级:5.71最长访问时间:15 ns
JESD-30 代码:R-PDSO-J44长度:28.575 mm
内存密度:524288 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:44字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX16封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:3.7592 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

CY7C1020B-15VCT 数据手册

 浏览型号CY7C1020B-15VCT的Datasheet PDF文件第2页浏览型号CY7C1020B-15VCT的Datasheet PDF文件第3页浏览型号CY7C1020B-15VCT的Datasheet PDF文件第4页浏览型号CY7C1020B-15VCT的Datasheet PDF文件第5页浏览型号CY7C1020B-15VCT的Datasheet PDF文件第6页浏览型号CY7C1020B-15VCT的Datasheet PDF文件第7页 
CY7C1020B  
32K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• High speed  
— tAA = 12, 15 ns  
• CMOS for optimum speed/power  
• Low active power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
— 825 mW (max.)  
• Low CMOS standby power (L version only)  
— 2.75 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in lead-free and non-lead-free 44-pin TSOP II  
and 44-pin (400-mil) SOJ packages  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Functional Description  
The CY7C1020B is a high-performance CMOS static RAM  
organized as 32,768 words by 16 bits. This device has an  
automatic power-down feature that significantly reduces  
power consumption when deselected.  
The CY7C1020B is available in standard 44-pin TSOP Type II  
and 44-pin 400-mil-wide SOJ packages.  
Logic Block Diagram  
Pin Configuration  
SOJ / TSOP II Pinout  
DATA IN DRIVERS  
Top View  
44  
1
NC  
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
A
2
7
A7  
A6  
OE  
A
1
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
A5  
A4  
A3  
A2  
A1  
32K x 16  
CE  
I/O1–I/O8  
RAM Array  
I/O  
7
1
16  
37  
36  
35  
34  
33  
I/O  
I/O  
8
2
3
15  
14  
13  
I/O9–I/O16  
9
10  
11  
12  
13  
I/O  
V
SS  
I/O  
4
CC  
V
SS  
A0  
V
V
CC  
32  
31  
30  
29  
28  
I/O  
I/O  
I/O  
5
6
7
8
12  
11  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
10  
9
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
BHE  
19  
A
A
14  
9
WE  
CE  
OE  
A
13  
20  
21  
22  
A
11  
10  
A
A
12  
24  
23  
NC  
NC  
BLE  
Selection Guide  
CY7C1020B-12  
CY7C1020B-15  
Maximum Access Time (ns)  
12  
140  
3
15  
130  
3
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
L
0.5  
0.5  
Cypress Semiconductor Corporation  
Document #: 38-05171 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 26, 2006  

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