009
CY7C109
CY7C1009
128K x 8 Static RAM
active HIGH chip enable (CE2), an active LOW output enable
(OE), and three-state drivers. Writing to the device is accom-
plished by taking chip enable one (CE1) and write enable (WE)
inputs LOW and chip enable two (CE2) input HIGH. Data on
the eight I/O pins (I/O0 through I/O7) is then written into the
location specified on the address pins (A0 through A16).
Features
• High speed
— tAA = 10 ns
• Low active power
— 1017 mW (max., 12 ns)
Reading from the device is accomplished by taking chip en-
able one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
• Low CMOS standby power
— 55 mW (max.), 4 mW (Low power version)
• 2.0V Data Retention (Low power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OEoptions
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Functional Description
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW chip enable (CE1), an
Logic Block Diagram
Pin Configurations
SOJ
Top View
V
NC
32
31
30
1
CC
A
16
A
15
2
3
A
14
CE
2
A
4
12
29
28
WE
5
A
A
A
A
13
A
8
A
7
27
26
6
6
5
7
9
25
24
23
22
21
A
A
3
8
9
10
11
12
13
A
4
11
OE
I/O
A
A
10
0
2
A
1
CE
I/O
I/O
INPUT BUFFER
1
7
6
A
0
I/O
I/O
I/O
I/O
I/O
0
1
2
1
20
19
A
0
A
1
I/O
5
14
15
16
I/O
I/O
18
17
4
2
A
2
GND
3
109–2
A
3
4
A
A11
A9
A8
1
2
32
31
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
I/O
I/O
I/O
3
4
5
512 x 256 x 8
ARRAY
A
5
6
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A13
A
7
8
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A
TSOP I
Top View
9
(not to scale)
I/O
10
11
12
13
14
15
16
6
7
POWER
DOWN
COLUMN
DECODER
CE
1
2
CE
I/O
WE
109–1
A3
OE
109–3
Selection Guide
7C109-10
7C109-12
7C109-15
7C109-20
7C109-25
7C109-35
7C1009-10 7C1009-12 7C1009-15 7C1009-20 7C1009-25 7C1009-35
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
10
195
10
2
12
185
10
2
15
155
10
2
20
140
10
25
135
10
35
125
10
—
—
—
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05032 Rev. **
Revised August 24, 2001