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CY7C09449PV-AC PDF预览

CY7C09449PV-AC

更新时间: 2024-09-16 22:15:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 总线控制器静态存储器PC
页数 文件大小 规格书
50页 906K
描述
128 Kb Dual-Port SRAM with PCI Bus Controller (PCI-DP)

CY7C09449PV-AC 数据手册

 浏览型号CY7C09449PV-AC的Datasheet PDF文件第2页浏览型号CY7C09449PV-AC的Datasheet PDF文件第3页浏览型号CY7C09449PV-AC的Datasheet PDF文件第4页浏览型号CY7C09449PV-AC的Datasheet PDF文件第5页浏览型号CY7C09449PV-AC的Datasheet PDF文件第6页浏览型号CY7C09449PV-AC的Datasheet PDF文件第7页 
09449PV  
CY7C09449PV-AC  
128 Kb Dual-Port SRAM with PCI Bus  
Controller (PCI-DP)  
A primary resource within the CY7C09449PV is its 128 Kb of  
dual-port memory. This memory is interfaced to both the PCI  
bus and to a local microprocessor bus. This shared memory  
Features  
• 128 Kb of dual-ported shared memory  
can be accessed as a target from both buses at the same time  
for inter-process communication. From either the local or PCI  
bus the CY7C09449PV can be directed to become a PCI bus  
master to move data into or out of the internal shared memory  
as a direct memory access (DMA). The CY7C09449PV can  
DMA across the PCI bus any number of 32-bit double words  
(DWORD), up to 16K bytes. It uses the full bursting capabilities  
of the PCI bus for maximum efficiency and can transfer data  
over the full 32-bit PCI address space.  
• Master and Target PCI Specification 2.2 compliant in-  
terface  
• Embedded host bridge capability  
• Direct interface to many microprocessors  
• I2O message transport unit; includes four 32-bit, 32-  
entry FIFO  
• Local bus clock rates up to 50 MHz  
• Single 3.3V Power Supply including compatibility with  
3V and 5V PCI Bus signaling  
The CY7C09449PV implements optional requirements of the  
PCI specification by selecting the optimum PCI command for  
each transaction it masters to the PCI bus. This maximizes  
overall efficiency of the system platform. PCI bridging func-  
tions (PCI-to-PCI and Host-to-PCI bridges) use the commands  
to enhance prefetch and cache coherency operations. The  
CY7C09449PV requests and gains access to the PCI bus as  
any master. It does not, within itself, include a PCI bus arbitra-  
tion function. Standard PC PCI buses include this function;  
embedded systems may need to implement this function.  
• 160-pin thin plastic quad flat package  
Introduction  
The CY7C09449PV is one of the PCI interface controllers in  
the Cypress Semiconductor PCI-DPfamily. The  
CY7C09449PV provides a PCI master/target interface with di-  
rect connections to many popular microprocessors. It provides  
128 Kb of dual-port SRAM that is used as shared memory  
between the local microprocessor and the PCI bus. An I2O  
message unit, complete with message queues and interrupt  
capability, is also provided. The CY7C09449PV allows the de-  
signer to interface an application to the PCI bus in a straight-  
forward, inexpensive way.  
The CY7C09449PV provides a direct access mechanism from  
the local bus to the PCI bus. With it, the local processor can  
direct the CY7C09449PV to run a PCI bus master cycle of any  
kind to any address. This means that the CY7C09449PV can  
run PCI configuration cycles allowing it to be used as a host  
bridge.  
Functional Overview  
The CY7C09449PV is composed of a number of shared re-  
sources that allow effective data movement between the local  
bus and the PCI bus.  
Table of Contents  
Features  
1
1
Introduction  
Functional Overview  
Pin Configuration  
Pin Description  
1
4
5
PCI Bus  
9
Local Bus  
12  
16  
27  
29  
41  
46  
48  
48  
Timing Diagrams  
I2C Serial Port and Auto-Configuration  
Operations Registers  
Performance Characteristics  
CY7C09449PV Operations  
Ordering Information  
Package Diagram  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06061 Rev. *A  
Revised December 27, 2002  

CY7C09449PV-AC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C09449PVA-AC CYPRESS

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128 Kb Dual-Port SRAM with PCI Bus Controller

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