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CY7C09579V-100AXC

更新时间： 2024-09-24 12:21:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
32页 688K
描述
3.3 V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM

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中文翻译

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CY7C09579V-100AXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFP-144针数：144
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.76
最长访问时间：12.5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：S-PQFP-G144JESD-609代码：e3
长度：20 mm内存密度：1179648 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端口数量：2端子数量：144
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP144,.87SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.001 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.385 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：20 mmBase Number Matches：1

CY7C09579V-100AXC 数据手册

 浏览型号CY7C09579V-100AXC的Datasheet PDF文件第2页浏览型号CY7C09579V-100AXC的Datasheet PDF文件第3页浏览型号CY7C09579V-100AXC的Datasheet PDF文件第4页浏览型号CY7C09579V-100AXC的Datasheet PDF文件第5页浏览型号CY7C09579V-100AXC的Datasheet PDF文件第6页浏览型号CY7C09579V-100AXC的Datasheet PDF文件第7页 
CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3  
Synchronous Dual-Port Static RAM  
V 16 K / 32 K × 36 FLEx36®  
CY7C09569V  
CY7C09579V  
3.3 V 16 K / 32 K × 36 FLEx36®  
Synchronous Dual-Port Static RAM  
Features  
Functional Description  
■ True dual-ported memory cells which allow simultaneous  
access of the same memory location  
The CY7C09569V and CY7C09579V are high-speed 3.3 V  
synchronous CMOS 16 K and 32 K × 36 dual-port static RAMs.  
Two ports are provided, permitting independent, simultaneous  
access for reads and writes to any location in memory.  
Registers on control, address, and data lines allow for minimal  
set-up and hold times. In pipelined output mode, data is regis-  
tered for decreased cycle time. Clock to data valid tCD2 = 5 ns  
(pipelined). Flow-through mode can also be used to bypass  
the pipelined output register to eliminate access latency. In  
flow-through mode data will be available tCD1 = 12.5 ns after  
the address is clocked into the device. Pipelined output or  
flow-through mode is selected via the FT/Pipe pin.  
■ Two flow-through/pipelined devices  
❐ 16 K × 36 organization (CY7C09569V)  
❐ 32 K × 36 organization (CY7C09579V)  
■ 0.25-micron CMOS for optimum speed/power  
■ Three modes  
❐ Flow-through  
❐ Pipelined  
❐ Burst  
Each port contains a burst counter on the input address  
register. The internal write pulse width is independent of the  
external R/W LOW duration. The internal write pulse is  
self-timed to allow the shortest possible cycle times.  
■ Bus-matching capabilities on right port  
(×36 to ×18 or ×9)  
■ Byte-select capabilities on left port  
■ 100-MHz pipelined operation  
A HIGH on CE for one clock cycle will power down the internal  
circuitry to reduce the static power consumption. In the  
pipelined mode, one cycle is required with CE LOW to  
reactivate the outputs.  
■ High-speed clock to data access 5/6 ns  
■ 3.3 V low operating power  
❐ Active = 250 mA (typical)  
❐ Standby = 10 μA (typical)  
Counter Enable Inputs are provided to stall the operation of the  
address input and utilize the internal address generated by the  
internal counter for fast interleaved memory applications. A  
port’s burst counter is loaded with the port’s Address Strobe  
(ADS). When the port’s Count Enable (CNTEN) is asserted,  
the address counter will increment on each LOW-to-HIGH  
transition of that port’s clock signal. This will read/write one  
word from/into each successive address location until CNTEN  
is deasserted. The counter can address the entire memory  
array and will loop back to the start. Counter Reset (CNTRST)  
is used to reset the burst counter.  
■ Fully synchronous interface for ease of use  
■ Burst counters increment addresses internally  
❐ Shorten cycle times  
❐ Minimize bus noise  
❐ Supported in flow-through and pipelined modes  
■ Counter address read back via I/O lines  
■ Single chip enable  
Parts are available in 144-pin Thin Quad Plastic Flatpack  
(TQFP), 144-pin Pb-free Thin Quad Plastic Flatpack (TQFP)  
and 172-ball Ball Grid Array (BGA) packages.  
■ Automatic power-down  
■ Commercial and industrial temperature ranges  
■ Compact package  
❐ 144-pin TQFP (20 × 20 × 1.4 mm)  
❐ 144-pin Pb-free TQFP (20 × 20 × 1.4 mm)  
❐ 172-ball BGA (1.0-mm pitch) (15 × 15 × 0.51 mm)  
Selection Guide  
CY7C09569V  
CY7C09579V  
Unit  
–100  
100  
5
–83  
83  
6
fMAX2 (pipelined)  
MHz  
ns  
Maximum access time (clock to data, pipelined)  
Typical operating current ICC  
250  
30  
240  
25  
10  
mA  
mA  
μA  
Typical standby current for ISB1 (both ports TTL level)  
Typical standby current for ISB3 (both ports CMOS level)  
10  
Cypress Semiconductor Corporation  
Document Number: 38-06054 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 23, 2011  
1234567...32

中文翻译

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CY7C09579V-100AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C09579V-83AC CYPRESS

完全替代

 3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C057V-15AXC CYPRESS

类似代替

 3.3V 16K/32K x 36 FLEx36⑩ Asynchronous Dual-P
CY7C057V-12AXC CYPRESS

类似代替

 3.3V 16K/32K x 36 FLEx36⑩ Asynchronous Dual-P

与CY7C09579V-100AXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C09579V-100BBC CYPRESS

获取价格

 		3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09579V-100BBXC CYPRESS

获取价格

 		Dual-Port SRAM, 32KX36, 12.5ns, CMOS, PBGA172, 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, ROH
CY7C09579V-67AC CYPRESS

获取价格

 		3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09579V-67AI CYPRESS

获取价格

 		Dual-Port SRAM, 128KX9, 8ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-144
CY7C09579V-67BAC CYPRESS

获取价格

 		Dual-Port SRAM, 32KX36, 8ns, CMOS, PBGA172, 15 X 15 MM, 0.51 MM HEIGHT, 1 MM PITCH, BGA-17
CY7C09579V-67BAI CYPRESS

获取价格

 		Dual-Port SRAM, 128KX9, 8ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, MINI, BGA-144
CY7C09579V-67BBC CYPRESS

获取价格

 		3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09579V-83AC CYPRESS

获取价格

 		3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09579V-83AI CYPRESS

获取价格

 		3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09579V-83AXC CYPRESS

获取价格

 		3.3 V 16 K / 32 K × 36 FLEx36® Synchronous

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