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CY7C09569V-83AI PDF预览

CY7C09569V-83AI

更新时间: 2024-09-17 13:00:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
30页 1118K
描述
Dual-Port SRAM, 16KX36, 6ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-144

CY7C09569V-83AI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-144针数:144
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:6 ns其他特性:AUTOMATIC POWER DOWN
最大时钟频率 (fCLK):83 MHzI/O 类型:COMMON
JESD-30 代码:S-PQFP-G144JESD-609代码:e0
长度:20 mm内存密度:589824 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
功能数量:1端口数量:2
端子数量:144字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP144,.87SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.001 A最小待机电流:3.15 V
子类别:SRAMs最大压摆率:0.385 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:20 mm
Base Number Matches:1

CY7C09569V-83AI 数据手册

 浏览型号CY7C09569V-83AI的Datasheet PDF文件第2页浏览型号CY7C09569V-83AI的Datasheet PDF文件第3页浏览型号CY7C09569V-83AI的Datasheet PDF文件第4页浏览型号CY7C09569V-83AI的Datasheet PDF文件第5页浏览型号CY7C09569V-83AI的Datasheet PDF文件第6页浏览型号CY7C09569V-83AI的Datasheet PDF文件第7页 
CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K  
FLEx36™ Synchronous Dual-Port Static RAM  
x 36  
CY7C09569V  
CY7C09579V  
3.3V 16K/32K x 36  
FLEx36™ Synchronous Dual-Port Static RAM  
• 3.3V Low operating power  
Features  
— Active = 250 mA (typical)  
• True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
— Standby = 10 μA (typical)  
• Fully synchronous interface for ease of use  
• Burst counters increment addresses internally  
— Shorten cycle times  
• Two Flow-Through/Pipelined devices  
— 16K x 36 organization (CY7C09569V)  
— 32K x 36 organization (CY7C09579V)  
• 0.25-micron CMOS for optimum speed/power  
• Three modes  
— Minimize bus noise  
— Supported in Flow-Through and Pipelined modes  
• Counter Address Read Back via I/O lines  
• Single Chip Enable  
— Flow-Through  
— Pipelined  
• Automatic power-down  
— Burst  
• Commercial and Industrial Temperature Ranges  
• Compact package  
• Bus-Matching Capabilities on Right Port  
(x36 to x18 or x9)  
• Byte-Select Capabilities on Left Port  
• 100-MHz Pipelined Operation  
— 144-Pin TQFP (20 x 20 x 1.4 mm)  
— 144-Pin Pb-Free TQFP (20 x 20 x 1.4 mm)  
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x 0.51 mm)  
• High-speed clock to data access 5/6/8 ns  
Logic Block Diagram  
R/WL  
R/WR  
OEL  
Left  
Right  
Port  
Control  
Logic  
OER  
CER  
Port  
Control  
Logic  
B0–B3  
CEL  
FT/PipeR  
FT/PipeL  
BE  
9
9
9
9
9
9
9
9
I/O0L–I/O8L  
9/18/36  
I/O9L–I/O17L  
I/O18L–I/O26L  
I/O27L–I/O35L  
Bus  
Match  
I/O  
Control  
I/O  
Control  
I/OR  
BM  
SIZE  
14/15  
14/15  
[1]  
[1]  
A0–A13/14L  
A0–A13/14R  
CLKR  
Counter/  
Address  
Register  
Decode  
Counter/  
CLKL  
True Dual-Ported  
Address  
Register  
Decode  
ADSL  
ADSR  
RAM Array  
CNTENL  
CNTRSTL  
CNTENR  
CNTRSTR  
Note:  
1. A –A for 16K; A –A for 32K devices.  
0
13  
0
14  
Cypress Semiconductor Corporation  
Document #: 38-06054 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised April 18, 2005  

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