Datasheet > CY7C09569V

CY7C09569V

更新时间： 2024-11-07 09:43:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
30页	1118K
描述
3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM

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CY7C09569V 数据手册

CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K

FLEx36™ Synchronous Dual-Port Static RAM

x 36

CY7C09569V

CY7C09579V

3.3V 16K/32K x 36

FLEx36™ Synchronous Dual-Port Static RAM

• 3.3V Low operating power

Features

— Active = 250 mA (typical)

• True dual-ported memory cells which allow simulta-

neous access of the same memory location

— Standby = 10 μA (typical)

• Fully synchronous interface for ease of use

• Burst counters increment addresses internally

— Shorten cycle times

• Two Flow-Through/Pipelined devices

— 16K x 36 organization (CY7C09569V)

— 32K x 36 organization (CY7C09579V)

• 0.25-micron CMOS for optimum speed/power

• Three modes

— Minimize bus noise

— Supported in Flow-Through and Pipelined modes

• Counter Address Read Back via I/O lines

• Single Chip Enable

— Flow-Through

— Pipelined

• Automatic power-down

— Burst

• Commercial and Industrial Temperature Ranges

• Compact package

• Bus-Matching Capabilities on Right Port

(x36 to x18 or x9)

• Byte-Select Capabilities on Left Port

• 100-MHz Pipelined Operation

— 144-Pin TQFP (20 x 20 x 1.4 mm)

— 144-Pin Pb-Free TQFP (20 x 20 x 1.4 mm)

— 172-Ball BGA (1.0-mm pitch) (15 x 15 x 0.51 mm)

• High-speed clock to data access 5/6/8 ns

Logic Block Diagram

R/W_L

R/W_R

OE_L

Left

Right

Port

Control

Logic

OE_R

CE_R

Port

Control

Logic

B₀–B₃

CE_L

FT/Pipe_R

FT/Pipe_L

I/O_0L–I/O_8L

9/18/36

I/O_9L–I/O_17L

I/O_18L–I/O_26L

I/O_27L–I/O_35L

Bus

Match

I/O

Control

I/O

Control

I/O_R

SIZE

14/15

[1]

A₀–A_13/14L

A₀–A_13/14R

CLK_R

Counter/

Address

Decode

Counter/

CLK_L

True Dual-Ported

Address

Decode

ADS_L

ADS_R

RAM Array

CNTEN_L

CNTRST_L

CNTEN_R

CNTRST_R

Note:

1. A –A for 16K; A –A for 32K devices.

Cypress Semiconductor Corporation

Document #: 38-06054 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised April 18, 2005

12 3 4 5 6 7...30

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与CY7C09569V相关器件

型号	品牌	获取价格	描述	数据表
CY7C09569V_12	CYPRESS	获取价格	3.3 V 16 K / 32 K Ã 36 FLEx36Â® Synchronous
CY7C09569V-100AC	CYPRESS	获取价格	3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09569V-100AXC	CYPRESS	获取价格	3.3 V 16 K / 32 K Ã 36 FLEx36Â® Synchronous
CY7C09569V-100BBC	CYPRESS	获取价格	3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09569V-133BAC	CYPRESS	获取价格	Dual-Port SRAM, 16KX36, 4.1ns, CMOS, PBGA172, 15 X 15 MM, 0.51 MM HEIGHT, 1 MM PITCH, BGA-
CY7C09569V-67AC	CYPRESS	获取价格	3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09569V-67AI	CYPRESS	获取价格	Dual-Port SRAM, 64KX9, 8ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-144
CY7C09569V-67BAC	CYPRESS	获取价格	Dual-Port SRAM, 16KX36, 8ns, CMOS, PBGA172, 15 X 15 MM, 0.51 MM HEIGHT, 1 MM PITCH, BGA-17
CY7C09569V-67BBC	CYPRESS	获取价格	3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM
CY7C09569V-83AC	CYPRESS	获取价格	3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM

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