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CY7C09349AV-9AXC PDF预览

CY7C09349AV-9AXC

更新时间: 2024-11-09 12:50:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
20页 351K
描述
3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM

CY7C09349AV-9AXC 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFP包装说明:LEAD FREE, PLASTIC, MS-026, TQFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.81Is Samacsys:N
最长访问时间:9 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e4长度:14 mm
内存密度:73728 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0005 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.23 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

CY7C09349AV-9AXC 数据手册

 浏览型号CY7C09349AV-9AXC的Datasheet PDF文件第2页浏览型号CY7C09349AV-9AXC的Datasheet PDF文件第3页浏览型号CY7C09349AV-9AXC的Datasheet PDF文件第4页浏览型号CY7C09349AV-9AXC的Datasheet PDF文件第5页浏览型号CY7C09349AV-9AXC的Datasheet PDF文件第6页浏览型号CY7C09349AV-9AXC的Datasheet PDF文件第7页 
CY7C09359AV3.3  
V 4 K/8 K × 18  
Synchronous Dual Port Static RAM  
CY7C09349AV  
CY7C09359AV  
3.3 V 4 K/8 K × 18  
Synchronous Dual Port Static RAM  
3.3  
V 4 K/8 K × 18 Synchronous Dual Port Static RAM  
High-speed clock to data access 9 and 12 ns (max)  
Features  
3.3 V low operating power  
Active = 135 mA (typical)  
Standby = 10 µA (typical)  
True dual ported memory cells which allow simultaneous  
access of the same memory location  
Two flow-through/pipelined devices  
4 K × 18 organization (CY7C09349AV)  
8 K × 18 organization (CY7C09359AV)  
Fully synchronous interface for easier operation  
Burst counters increment addresses internally  
Shorten cycle times  
Minimize bus noise  
Three modes  
Flow-through  
Pipelined  
Burst  
Supported in flow-through and pipelined modes  
Dual chip enables for easy depth expansion  
Upper and lower byte controls for bus matching  
Automatic power-down  
Pipelined output mode on both ports allows fast 67-MHz  
operation  
0.35-micron complementary metal oxide semiconductor  
(CMOS) for optimum speed/power  
Available in 100-pin thin quad flat pack (TQFP)  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
1
1
CE1L  
LBL  
CE1R  
LBR  
0
0
0/1  
0/1  
OEL  
OER  
1b 0b 1a 0a  
0a 1a 0b 1b  
0/1  
0/1  
b
a
a
b
FT/PipeL  
FT/PipeR  
9
9
9
9
I/O9L–I/O17L  
I/O9R–I/O17R  
I/O  
Control  
I/O  
Control  
I/O0L–I/O8L  
I/O0R–I/O8R  
12/13  
12/13  
[1]  
[1]  
A0L–A  
A0R–A11/12R  
11/12L  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLKL  
ADSL  
CLKR  
ADSR  
True Dual Ported  
RAM Array  
CNTENL  
CNTENR  
CNTRSTR  
CNTRSTL  
Note  
1. A –A for 4 K; A –A for 8 K devices.  
0
11  
0
12  
Cypress Semiconductor Corporation  
Document Number: 001-63888 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 28, 2011  

CY7C09349AV-9AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C09349AV-12AXC CYPRESS

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3.3 V 4 K/8 K × 18 Synchronous Dual Port Sta
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4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
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3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM

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