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CY7C09349AV-12AC PDF预览

CY7C09349AV-12AC

更新时间: 2024-11-08 22:25:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 323K
描述
3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM

CY7C09349AV-12AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP100,.63SQ,20
针数:100Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.82
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:73728 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:4096 words字数代码:4000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.18 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

CY7C09349AV-12AC 数据手册

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1
CY7C09349AV  
CY7C09359AV  
3.3V 4K/8K x 18  
Synchronous Dual-Port Static RAM  
• High-speed clock to data access 9 and 12 ns (max.)  
• 3.3V Low operating power  
Features  
True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
— Active = 135 mA (typical)  
— Standby = 10 A (typical)  
µ
• Two Flow-Through/Pipelined devices  
— 4K x 18 organization (CY7C09349AV)  
— 8K x 18 organization (CY7C09359AV)  
• Three Modes  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
— Shorten cycle times  
— Minimize bus noise  
— Flow-Through  
— Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Upper and lower byte controls for bus matching  
• Automatic power-down  
— Pipelined  
— Burst  
• Pipelinedoutputmodeonbothportsallowsfast83-MHz  
operation  
• Commercial and Industrial temperature ranges  
• 0.35-micron CMOS for optimum speed/power  
Available in 100-pin TQFP  
v
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
CE  
CE  
0L  
1L  
0R  
1R  
1
1
0
0
0/1  
0/1  
LB  
LB  
L
R
OE  
OE  
L
R
1b 0b 1a 0a  
0a 1a 0b 1b  
a b 0/1  
0/1  
b
a
FT/Pipe  
FT/Pipe  
L
R
9
9
9
9
I/O –I/O  
I/O –I/O  
9R 17R  
9L  
17L  
8L  
I/O  
Control  
I/O  
Control  
I/O –I/O  
I/O –I/O  
0L  
0R  
8R  
12/13  
12/13  
[1]  
A
–A[1]  
A
–A  
0L  
11/12L  
0R 11/12R  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLK  
CLK  
ADS  
L
R
R
R
R
True Dual-Ported  
RAM Array  
ADS  
L
CNTEN  
CNTEN  
L
CNTRST  
CNTRST  
L
Notes:  
1. A0–A11 for 4K; A0–A12 for 8K devices.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 13, 2000  

CY7C09349AV-12AC 替代型号

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CY7C09349AV-9AXC CYPRESS

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