Datasheet > CY7C09159A

CY7C09159A

更新时间： 2024-09-19 00:01:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	331K
描述
8K/16K x 9 Synchronous Dual-Port Static RAM

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中文翻译

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数据手册

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CY7C09159A 数据手册

25/0251

CY7C09159A

CY7C09169A

8K/16K x 9

Synchronous Dual-Port Static RAM

• High-speedclocktodataaccess6.5^[1]/7.5/9/12ns(max.)

• Low operating power

Features

• True dual-ported memory cells which allow simulta-

neous access of the same memory location

—Active = 200 mA (typical)

—Standby = 0.05 mA (typical)

• Two Flow-Through/Pipelined devices

— 8K x 9 organization (CY7C09159A)

— 16K x 9 organization (CY7C09169A)

• Three Modes

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

—Shorten cycle times

—Minimize bus noise

— Flow-Through

—Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Automatic power-down

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP

— Pipelined

— Burst

• Pipelined output mode on both ports allows fast

100-MHz cycle time

• 0.35-micron CMOS for optimum speed/power

Logic Block Diagram

R/W_L

OE_L

R/W_R

OE_R

CE_0L

CE_0R

CE_1L

CE_1R

0/1

FT/Pipe_L

FT/Pipe_R

I/O_0L–I/O_8L

I/O_0R–I/O_8R

I/O

Control

13/14

[2]

A₀–A_12/13L

A₀–A_12/13R

Counter/

Address

Decode

Counter/

Address

Decode

CLK_L

CLK_R

ADS_R

True Dual-Ported

RAM Array

ADS_L

CNTEN_L

CNTRST_L

CNTEN_R

CNTRST_R

Notes:

1. See page 6 for Load Conditions.

2. A₀–A₁₂for 8K; A₀–A₁₃for 16K.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06047 Rev. *A

Revised December 27, 2002

12 3 4 5 6 7...18

中文翻译

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