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CY7C09159AV_11 PDF预览

CY7C09159AV_11

更新时间: 2024-09-19 12:21:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 434K
描述
3.3-V 8 K × 9 Synchronous Dual Port Static RAM

CY7C09159AV_11 数据手册

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CY7C09169AVTITLE  
CY7C09159AV  
3.3-V 8 K × 9  
Synchronous Dual Port Static RAM  
3.3 V Low operating power  
Active = 135 mA (typical)  
Standby = 10 μA (typical)  
Features  
True dual-ported memory cells which allow simultaneous  
access of the same memory location  
Fully synchronous interface for easier operation  
Flow-through/Pipelined device  
8 K × 9 organization (CY7C09159AV)  
Burst counters increment addresses internally  
Shorten cycle times  
Minimize bus noise  
Three Modes  
Flow-through  
Pipelined  
Burst  
Supported in Flow-through and Pipelined modes  
Dual chip enables for easy depth expansion  
Automatic power-down  
Pipelined output mode on both ports allows fast 67-MHz  
operation  
Commercial temperature ranges  
0.35-micron complementary metal oxide semiconductor  
(CMOS) for optimum speed/power  
Available in 100-pin thin quad plastic flatpack (TQFP)  
Pb-free packages available  
High-speed clock to data access 9 ns (max.)  
Logic Block Diagram  
R/WL  
OEL  
R/WR  
OER  
CE0L  
CE0R  
1
1
CE1L  
CE1R  
0
0
0/1  
0/1  
1
0
0
1
0/1  
0/1  
FT/PipeL  
FT/PipeR  
9
9
I/O0LI/O8L  
I/O0RI/O8R  
I/O  
Control  
I/O  
Control  
13  
13  
A0A12L  
CLKL  
A0A12R  
CLKR  
Counter/  
Counter/  
Address  
Register  
Decode  
Address  
Register  
Decode  
True Dual-Ported  
ADSL  
ADSR  
RAM Array  
CNTENL  
CNTRSTL  
CNTENR  
CNTRSTR  
Cypress Semiconductor Corporation  
Document Number: 38-06053 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 8, 2011  

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