Datasheet > CY7C09169

CY7C09169

更新时间： 2024-11-09 21:55:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	454K
描述
8K/16K x 9 Synchronous Dual-Port Static RAM

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中文翻译

获取价格

数据手册

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CY7C09169 数据手册

fax id: 5218

CY7C09159

CY7C09169

PRELIMINARY

8K/16K x 9

Synchronous Dual-Port Static RAM

• High-speed clock to data access 6.5/7.5/12 ns (max.)

• Low operating power

Features

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

— Active= 200 mA (typical)

— Standby= 0.05 mA (typical)

• 2 Flow-Through/Pipelined devices

— 8K x 9 organization (CY7C09159)

— 16K x 9 organization (CY7C09169)

• 3 Modes

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

— Shorten cycle times

— Minimize bus noise

— Flow-Through

— Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Automatic power-down

— Pipelined

— Burst

• Pipelined output mode on both ports allows fast

100-MHz cycle time

• Commercial and Industrial temperature ranges

Available in 100-pin TQFP

•

• 0.35-micron CMOS for optimum speed/power

Logic Block Diagram

R/W

0/1

FT/Pipe

I/O –I/O

I/O

Control

13/14

[1]

A –A

0 12/13R

12/13L

Counter/

Address

Decode

Counter/

Address

Decode

CLK

ADS

True Dual-Ported

RAM Array

ADS

CNTEN

CNTRST

Note:

1. A₀–A₁₂for 8K; A₀–A₁₃for 16K.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

November 1997 - Revised June 5, 1998

12 3 4 5 6 7...15

中文翻译

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