Datasheet > CY7C09169AV

CY7C09169AV

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	320K
描述
3.3V 8K/16K x 9 Synchronous Dual Port Static RAM

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数据手册

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CY7C09169AV 数据手册

25/0251

CY7C09159AV

CY7C09169AV

3.3V 8K/16K x 9

Synchronous Dual Port Static RAM

• High-speed clock to data access 9 and 12 ns (max.)

• 3.3V Low operating power

Features

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

—Active = 135 mA (typical)

—Standby = 10 µA (typical)

• Two Flow-Through/Pipelined devices

— 8K x 9 organization (CY7C09159AV)

— 16K x 9 organization (CY7C09169AV)

• Three Modes

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

—Shorten cycle times

—Minimize bus noise

— Flow-Through

—Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Automatic power-down

— Pipelined

— Burst

• Pipelinedoutputmodeonbothportsallowsfast83-MHz

operation

• Commercial and industrial temperature ranges

• Available in 100-pin TQFP

• 0.35-micron CMOS for optimum speed/power

Logic Block Diagram

R/W_L

OE_L

R/W_R

OE_R

CE_0L

CE_1L

CE_0R

CE_1R

0/1

FT/Pipe_L

FT/Pipe_R

I/O_0L−I/O_8L

I/O_0R−I/O_8R

I/O

Control

13/14

[1]

A₀−A_12/13L

A₀−A_12/13R

Counter/

Address

Decode

Counter/

Address

Decode

CLK_L

CLK_R

ADS_R

True Dual-Ported

RAM Array

ADS_L

CNTEN_L

CNTRST_L

CNTEN_R

CNTRST_R

Notes:

1. A₀−A₁₂for 8K; A₀−A₁₃for 16K.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06053 Rev. **

Revised September 21, 2001

12 3 4 5 6 7...17

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