25/0251
CY7C09089/99
CY7C09189/99
64K/128K x 8/9
Synchronous Dual-Port Static RAM
• Low operating power
Features
—Active = 195 mA (typical)
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
—Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
—Shorten cycle times
• Six Flow-Through/Pipelined devices
— 64K x 8/9 organizations (CY7C09089/189)
— 128K x 8/9 organizations (CY7C09099/199)
• Three Modes
—Minimize bus noise
—Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 100-
MHz cycle time
• Pin-compatibleandfunctionallyequivalenttoIDT70908
and IDT709089
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1]/7.5/9/12 ns
(max.)
Logic Block Diagram
R/WL
OEL
R/WR
OER
CE0L
CE0R
1
1
CE1L
CE1R
0
0
0/1
0/1
1
0
0
1
0/1
0/1
FT/PipeL
FT/PipeR
[2]
[2]
8/9
8/9
I/O0L–I/O7/8L
I/O0R–I/O7/8R
I/O
I/O
Control
Control
16/17
16/17
[3]
[3]
A0–A15/16L
A0–A
15/16R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
CLKL
CLKR
True Dual-Ported
RAM Array
ADSL
ADSR
CNTENL
CNTRSTL
CNTENR
CNTRSTR
Notes:
1. See page 7 for Load Conditions.
2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3. A0–A15 for 64K; and A0–A16 for 128K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06039 Rev. *A
Revised December 27, 2002