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CY7C09189-12AI PDF预览

CY7C09189-12AI

更新时间: 2024-11-07 13:01:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 337K
描述
Dual-Port SRAM, 64KX9, 12ns, CMOS, PQFP100, PLASTIC, TQFP-100

CY7C09189-12AI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.92Is Samacsys:N
最长访问时间:12 ns其他特性:AUTOMATIC POWER DOWN
最大时钟频率 (fCLK):50 MHzI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:589824 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
功能数量:1端口数量:2
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX9输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63X.87
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0005 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.375 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY7C09189-12AI 数据手册

 浏览型号CY7C09189-12AI的Datasheet PDF文件第2页浏览型号CY7C09189-12AI的Datasheet PDF文件第3页浏览型号CY7C09189-12AI的Datasheet PDF文件第4页浏览型号CY7C09189-12AI的Datasheet PDF文件第5页浏览型号CY7C09189-12AI的Datasheet PDF文件第6页浏览型号CY7C09189-12AI的Datasheet PDF文件第7页 
25/0251  
CY7C09089/99  
CY7C09189/99  
64K/128K x 8/9  
Synchronous Dual-Port Static RAM  
• Low operating power  
Features  
Active = 195 mA (typical)  
• True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
Standby = 0.05 mA (typical)  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
Shorten cycle times  
• Six Flow-Through/Pipelined devices  
— 64K x 8/9 organizations (CY7C09089/189)  
— 128K x 8/9 organizations (CY7C09099/199)  
• Three Modes  
Minimize bus noise  
Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Automatic power-down  
• Commercial and Industrial temperature ranges  
• Available in 100-pin TQFP  
— Flow-Through  
— Pipelined  
— Burst  
• Pipelined output mode on both ports allows fast 100-  
MHz cycle time  
Pin-compatibleandfunctionallyequivalenttoIDT70908  
and IDT709089  
• 0.35-micron CMOS for optimum speed/power  
• High-speed clock to data access 6.5[1]/7.5/9/12 ns  
(max.)  
Logic Block Diagram  
R/WL  
OEL  
R/WR  
OER  
CE0L  
CE0R  
1
1
CE1L  
CE1R  
0
0
0/1  
0/1  
1
0
0
1
0/1  
0/1  
FT/PipeL  
FT/PipeR  
[2]  
[2]  
8/9  
8/9  
I/O0LI/O7/8L  
I/O0RI/O7/8R  
I/O  
I/O  
Control  
Control  
16/17  
16/17  
[3]  
[3]  
A0A15/16L  
A0A  
15/16R  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLKL  
CLKR  
True Dual-Ported  
RAM Array  
ADSL  
ADSR  
CNTENL  
CNTRSTL  
CNTENR  
CNTRSTR  
Notes:  
1. See page 7 for Load Conditions.  
2. I/O0I/O7 for x8 devices; I/O0I/O8 for x9 devices.  
3. A0A15 for 64K; and A0A16 for 128K devices.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06039 Rev. *A  
Revised December 27, 2002  

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