Datasheet > CY7C09189V-6AC

CY7C09189V-6AC

更新时间： 2024-01-23 21:49:01

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	335K
描述
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

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数据手册

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CY7C09189V-6AC 数据手册

25/0251

CY7C09079V/89V/99V

CY7C09179V/89V/99V

3.3V 32K/64K/128K x 8/9

Synchronous Dual-Port Static RAM

• High-speed clock to data access 6.5^[1]/7.5^[1]/9/12 ns

Features

(max.)

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 3.3V low operating power

—Active= 115 mA (typical)

• 6 Flow-Through/Pipelined devices

— 32K x 8/9 organizations (CY7C09079V/179V)

— 64K x 8/9 organizations (CY7C09089V/189V)

— 128K x 8/9 organizations (CY7C09099V/199V)

• 3 Modes

—Standby= 10 µA (typical)

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

—Shorten cycle times

—Minimize bus noise

— Flow-Through

—Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Automatic power-down

— Pipelined

— Burst

• Pipelined output mode on both ports allows fast

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP

100-MHz operation

• 0.35-micron CMOS for optimum speed/power

Logic Block Diagram

R/W_L

OE_L

R/W_R

OE_R

CE_0L

CE_0R

CE_1L

CE_1R

0/1

FT/Pipe_L

FT/Pipe_R

[2]

8/9

I/O_0L–I/O_7/8L

I/O_0R–I/O_7/8R

I/O

Control

15/16/17

[3]

A₀–A_14/15/16L

A₀–A

14/15/16R

Counter/

Address

Decode

Counter/

Address

Decode

CLK_L

CLK_R

True Dual-Ported

RAM Array

ADS_L

ADS_R

CNTEN_L

CNTRST_L

CNTEN_R

CNTRST_R

Notes:

1. See page 6 for Load Conditions.

2. I/O₀–I/O₇for x8 devices, I/O₀–I/O₈for x9 devices.

3. A₀–A₁₄for 32K, A₀–A₁₅for 64K, and A₀–A₁₆for 128K devices.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06043 Rev. *A

Revised December 27, 2002

12 3 4 5 6 7...18

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