Datasheet > 存储 > SRAM> CY7C09199V-9AXC

CY7C09199V-9AXC

更新时间： 2024-11-07 03:13:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	537K
描述
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

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中文翻译

获取价格

数据手册

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CY7C09199V-9AXC 数据手册

CY7C09079V/89V/99V

CY7C09179V/89V/99V

CY7C09079V/89V/99V

CY7C09179V/89V/99V

3.3V 32K/64K/128K x 8/9

Synchronous Dual-Port Static RAM

• High-speed clock to data access 6.5^[1]/7.5^[1]/9/12 ns

(max.)

Features

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 3.3V low operating power

— Active= 115 mA (typical)

• 6 Flow-Through/Pipelined devices

— 32K x 8/9 organizations (CY7C09079V/179V)

— 64K x 8/9 organizations (CY7C09089V/189V)

— 128K x 8/9 organizations (CY7C09099V/199V)

• 3 Modes

— Standby= 10 µA (typical)

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

— Shorten cycle times

— Minimize bus noise

— Flow-Through

— Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Automatic power-down

— Pipelined

— Burst

• Pipelined output mode on both ports allows fast

100-MHz operation

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP

• 0.35-micron CMOS for optimum speed/power

• Pb-Free packages available

Logic Block Diagram

R/W_L

OE_L

R/W_R

OE_R

CE_0L

CE_0R

CE_1L

CE_1R

0/1

FT/Pipe_L

FT/Pipe_R

8/9

[2]

7/8R

I/O_0L–I/O_7/8L

I/O_0R–I/O

I/O

Control

I/O

Control

15/16/17

[3]

A₀–A

CLK_L

A₀–A

14/15/16R

14/15/16L

Counter/

Address

Decode

CLK_R

Address

Decode

True Dual-Ported

ADS_L

ADS_R

RAM Array

CNTEN_L

CNTRST_L

CNTEN_R

CNTRST_R

Notes:

1. See page 6 for Load Conditions.

2. I/O –I/O for x8 devices, I/O –I/O for x9 devices.

3. A –A for 32K, A –A for 64K, and A –A for 128K devices.

Cypress Semiconductor Corporation

Document #: 38-06043 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised May 18, 2005

12 3 4 5 6 7...18

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